Fix interrupt stack handlings for ARM SMP

arch/arm/src/common/arm_checkstack.c

@@ -245,7 +245,7 @@ ssize_t up_check_stack_remain(void)
 size_t up_check_intstack(void)
 {
 #ifdef CONFIG_SMP
-  return do_stackcheck((FAR void *)arm_intstack_base(),
+  return do_stackcheck((FAR void *)arm_intstack_alloc(),
                         INT32_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK));
 #else
   return do_stackcheck((FAR void *)&g_intstackalloc,

arch/arm/src/common/arm_initialize.c

@@ -62,13 +62,17 @@
 static inline void up_color_intstack(void)
 {
 #ifdef CONFIG_SMP
-  uint32_t *ptr = (uint32_t *)arm_intstack_base();
+  uint32_t *ptr = (uint32_t *)arm_intstack_alloc();
 #else
   uint32_t *ptr = (uint32_t *)&g_intstackalloc;
 #endif
   ssize_t size;
 
+#ifdef CONFIG_SMP
+  for (size = ((CONFIG_ARCH_INTERRUPTSTACK & ~3) * CONFIG_SMP_NCPUS);
+#else
   for (size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
+#endif
        size > 0;
        size -= sizeof(uint32_t))
     {

arch/arm/src/cxd56xx/chip.h

@@ -56,6 +56,7 @@
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
 #  include "cxd56_cpuindex.h"
+#  include "cxd56_irq.h"
 #endif
 
 /****************************************************************************
@@ -75,43 +76,13 @@
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
   .macro  setintstack, tmp1, tmp2
-#if CONFIG_SMP_NCPUS > 1
   ldr \tmp1, =CXD56_ADSP_PID
   ldr \tmp1, [\tmp1, 0]
   sub \tmp1, 2                   /* tmp1 = getreg32(CXD56_ADSP_PID) - 2 */
   ldr \tmp2, =g_cpu_intstack_top
   ldr sp, [\tmp2, \tmp1, lsl #2] /* sp = g_cpu_intstack_top[tmp1] */
-#endif
   .endm
 #endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
 
 #endif /* __ASSEMBLY__  */
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-#if defined(__cplusplus)
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
-/****************************************************************************
- * Public Functions Prototypes
- ****************************************************************************/
-
-#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-uintptr_t arm_intstack_base(void);
-#endif
-
-#undef EXTERN
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
 #endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_H */

arch/arm/src/cxd56xx/cxd56_irq.c

@@ -72,10 +72,7 @@
 
 #define INTC_EN(n) (CXD56_INTC_BASE + 0x10 + (((n) >> 5) << 2))
 
-/* Interrupt stack definitions for SMP */
-
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-#  define INTSTACK_SIZE  CONFIG_ARCH_INTERRUPTSTACK
 #  define INTSTACK_ALLOC (CONFIG_SMP_NCPUS * INTSTACK_SIZE)
 #endif
 
@@ -115,17 +112,17 @@ static uint64_t g_intstack_alloc[INTSTACK_ALLOC >> 3];
 
 const uint32_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] =
 {
-  (uint32_t)g_intstack_alloc + INTSTACK_SIZE,
+  (uint32_t)g_intstack_alloc + INTSTACK_SIZE - 8,
 #if CONFIG_SMP_NCPUS > 1
-  (uint32_t)g_intstack_alloc + (2 * INTSTACK_SIZE),
+  (uint32_t)g_intstack_alloc + (2 * INTSTACK_SIZE) - 8,
 #if CONFIG_SMP_NCPUS > 2
-  (uint32_t)g_intstack_alloc + (3 * INTSTACK_SIZE),
+  (uint32_t)g_intstack_alloc + (3 * INTSTACK_SIZE) - 8,
 #if CONFIG_SMP_NCPUS > 3
-  (uint32_t)g_intstack_alloc + (4 * INTSTACK_SIZE),
+  (uint32_t)g_intstack_alloc + (4 * INTSTACK_SIZE) - 8,
 #if CONFIG_SMP_NCPUS > 4
-  (uint32_t)g_intstack_alloc + (5 * INTSTACK_SIZE),
+  (uint32_t)g_intstack_alloc + (5 * INTSTACK_SIZE) - 8,
 #if CONFIG_SMP_NCPUS > 5
-  (uint32_t)g_intstack_alloc + (6 * INTSTACK_SIZE),
+  (uint32_t)g_intstack_alloc + (6 * INTSTACK_SIZE) - 8,
 #endif /* CONFIG_SMP_NCPUS > 5 */
 #endif /* CONFIG_SMP_NCPUS > 4 */
 #endif /* CONFIG_SMP_NCPUS > 3 */
@@ -647,17 +644,29 @@ int up_prioritize_irq(int irq, int priority)
  *
  * Description:
  *   Return a pointer to the "base" the correct interrupt stack allocation
- *   for the  current CPU.
+ *   for the current CPU. NOTE: Here, the base means "top" of the stack
  *
  ****************************************************************************/
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
 uintptr_t arm_intstack_base(void)
 {
-  uintptr_t base = (uintptr_t)g_intstack_alloc;
-  uint32_t cpu = up_cpu_index();
-  base += cpu * INTSTACK_SIZE;
+  return g_cpu_intstack_top[up_cpu_index()];
+}
+#endif
 
-  return base;
+/****************************************************************************
+ * Name: arm_intstack_alloc
+ *
+ * Description:
+ *   Return a pointer to the "alloc" the correct interrupt stack allocation
+ *   for the current CPU.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+uintptr_t arm_intstack_alloc(void)
+{
+  return g_cpu_intstack_top[up_cpu_index()] - (INTSTACK_SIZE - 8);
 }
 #endif

arch/arm/src/cxd56xx/cxd56_irq.h

@@ -48,6 +48,12 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+/* The size of one interrupt stack.  This is the configured value aligned
+ * the 8-bytes as required by the ARM EABI.
+ */
+
+#define INTSTACK_SIZE  (CONFIG_ARCH_INTERRUPTSTACK & ~7)
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
@@ -67,14 +73,15 @@ extern "C"
 #define EXTERN extern
 #endif
 
-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions Prototypes
  ****************************************************************************/
 
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+EXTERN uintptr_t arm_intstack_base(void);
+EXTERN uintptr_t arm_intstack_alloc(void);
+#endif
+
 #undef EXTERN
 #if defined(__cplusplus)
 }

arch/arm/src/imx6/chip.h

@@ -61,30 +61,13 @@
 
 #define CHIP_MPCORE_VBASE IMX_ARMMP_VSECTION
 
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-#ifdef __ASSEMBLY__
-
-#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-	.globl	g_irqstack_top
-	.globl	g_fiqstack_top
-#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
-
-#endif /* __ASSEMBLY__ */
-
 /****************************************************************************
  * Macro Definitions
  ****************************************************************************/
 
 #ifdef __ASSEMBLY__
 
-/***************************************************************************
+/****************************************************************************
  * Name: cpuindex
  *
  * Description:
@@ -93,30 +76,30 @@
  ****************************************************************************/
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-	.macro	cpuindex, index
-	mrc		p15, 0, \index, c0, c0, 5	/* Read the MPIDR */
-	and		\index, \index, #3			/* Bits 0-1=CPU ID */
-	.endm
+  .macro  cpuindex, index
+  mrc  p15, 0, \index, c0, c0, 5  /* Read the MPIDR */
+  and  \index, \index, #3         /* Bits 0-1=CPU ID */
+  .endm
 #endif
 
-/***************************************************************************
+/****************************************************************************
  * Name: setirqstack
  *
  * Description:
  *   Set the current stack pointer to the  -"top" of the IRQ interrupt
  *   stack for the current CPU.
  *
- ***************************************************************************/
+ ****************************************************************************/
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-	.macro	setirqstack, tmp1, tmp2
-	mrc		p15, 0, \tmp1, c0, c0, 5	/* tmp1=MPIDR */
-	and		\tmp1, \tmp1, #3			/* Bits 0-1=CPU ID */
-	ldr		\tmp2, =g_irqstack_top		/* tmp2=Array of IRQ stack pointers */
-	lsls	\tmp1, \tmp1, #2			/* tmp1=Array byte offset */
-	add		\tmp2, \tmp2, \tmp1			/* tmp2=Offset address into array */
-	ldr		sp, [\tmp2, #0]				/* sp=Address in stack allocation */
-	.endm
+  .macro  setirqstack, tmp1, tmp2
+  mrc  p15, 0, \tmp1, c0, c0, 5  /* tmp1=MPIDR */
+  and  \tmp1, \tmp1, #3          /* Bits 0-1=CPU ID */
+  ldr  \tmp2, =g_irqstack_top    /* tmp2=Array of IRQ stack pointers */
+  lsls \tmp1, \tmp1, #2          /* tmp1=Array byte offset */
+  add  \tmp2, \tmp2, \tmp1       /* tmp2=Offset address into array */
+  ldr  sp, [\tmp2, #0]           /* sp=Address in stack allocation */
+  .endm
 #endif
 
 /****************************************************************************
@@ -129,67 +112,16 @@
  ****************************************************************************/
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-	.macro	setfiqstack, tmp1, tmp2
-	mrc		p15, 0, \tmp1, c0, c0, 5	/* tmp1=MPIDR */
-	and		\tmp1, \tmp1, #3			/* Bits 0-1=CPU ID */
-	ldr		\tmp2, =g_fiqstack_top		/* tmp2=Array of FIQ stack pointers */
-	lsls	\tmp1, \tmp1, #2			/* tmp1=Array byte offset */
-	add		\tmp2, \tmp2, \tmp1			/* tmp2=Offset address into array */
-	ldr		sp, [\tmp2, #0]				/* sp=Address in stack allocation */
-	.endm
+  .macro  setfiqstack, tmp1, tmp2
+  mrc  p15, 0, \tmp1, c0, c0, 5  /* tmp1=MPIDR */
+  and  \tmp1, \tmp1, #3          /* Bits 0-1=CPU ID */
+  ldr  \tmp2, =g_fiqstack_top    /* tmp2=Array of FIQ stack pointers */
+  lsls \tmp1, \tmp1, #2          /* tmp1=Array byte offset */
+  add  \tmp2, \tmp2, \tmp1       /* tmp2=Offset address into array */
+  ldr  sp, [\tmp2, #0]           /* sp=Address in stack allocation */
+  .endm
 #endif
 
 #endif /* __ASSEMBLY__ */
 
-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/****************************************************************************
- * Name: arm_intstack_base
- *
- * Description:
- *   Return a pointer to the "base" the correct interrupt stack allocation
- *   for the  current CPU.
- *
- ****************************************************************************/
-
-#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-static inline uintptr_t arm_intstack_base(void)
-{
-  uintptr_t base = (uintptr_t)g_irqstack_alloc;
-#if CONFIG_SMP_NCPUS > 1
-  uint32_t cpu = up_cpu_index();
-
-  base += cpu * INTSTACK_SIZE;
-#endif
-
-  return base;
-}
-#endif
-
-/****************************************************************************
- * Name: arm_intstack_top
- *
- * Description:
- *   Return a pointer to the "top" the correct interrupt stack for the
- *   current CPU.
- *
- ****************************************************************************/
-
-#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
-static inline uintptr_t arm_intstack_top(void)
-{
-  return arm_intstack_base() + INTSTACK_SIZE;
-}
-#endif
-
-#endif /* !__ASSEMBLY__ */
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
 #endif /* __ARCH_ARM_SRC_IMX6_CHIP_H */

arch/arm/src/imx6/imx_irq.c

@@ -88,15 +88,15 @@ uint64_t g_fiqstack_alloc[INTSTACK_ALLOC >> 3];
 
 uintptr_t g_irqstack_top[CONFIG_SMP_NCPUS] =
 {
-  (uintptr_t)g_irqstack_alloc + INTSTACK_SIZE,
+  (uintptr_t)g_irqstack_alloc + INTSTACK_SIZE - 8,
 #if CONFIG_SMP_NCPUS > 1
-  (uintptr_t)g_irqstack_alloc + 2 * INTSTACK_SIZE,
+  (uintptr_t)g_irqstack_alloc + (2 * INTSTACK_SIZE) - 8,
 #endif
 #if CONFIG_SMP_NCPUS > 2
-  (uintptr_t)g_irqstack_alloc + 3 * INTSTACK_SIZE,
+  (uintptr_t)g_irqstack_alloc + (3 * INTSTACK_SIZE) - 8,
 #endif
 #if CONFIG_SMP_NCPUS > 3
-  (uintptr_t)g_irqstack_alloc + 4 * INTSTACK_SIZE
+  (uintptr_t)g_irqstack_alloc + (4 * INTSTACK_SIZE) - 8
 #endif
 };
 
@@ -186,3 +186,35 @@ void up_irqinitialize(void)
   up_irq_enable();
 #endif
 }
+
+/****************************************************************************
+ * Name: arm_intstack_base
+ *
+ * Description:
+ *   Return a pointer to the "base" the correct interrupt stack allocation
+ *   for the current CPU. NOTE: Here, the base means "top" of the stack
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+uintptr_t arm_intstack_base(void)
+{
+  return g_irqstack_top[up_cpu_index()];
+}
+#endif
+
+/****************************************************************************
+ * Name: arm_intstack_alloc
+ *
+ * Description:
+ *   Return a pointer to the "alloc" the correct interrupt stack allocation
+ *   for the current CPU.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
+uintptr_t arm_intstack_alloc(void)
+{
+  return g_irqstack_top[up_cpu_index()] - (INTSTACK_SIZE - 8);
+}
+#endif