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[BACKPORT #2309] Fix armv7-a L2CC and apply the code to the sabre-6quad board #2342

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Merged
Ouss4 merged 10 commits into from
Nov 19, 2020
Merged

[BACKPORT #2309] Fix armv7-a L2CC and apply the code to the sabre-6quad board #2342

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a07c614
arch: armv7-a: Fix style warnings in arm_l2cc_pl310.c
masayuki2009 Nov 16, 2020
327414c
arch: armv7-a: Fix style warnings in l2cc_pl310.h
masayuki2009 Nov 16, 2020
9020686
arch: armv7-a: Fix compile errors in arm_l2cc_pl310.c
masayuki2009 Nov 16, 2020
79ef13f
arch: armv7-a: Fix comile errors in l2cc_pl310.h
masayuki2009 Nov 16, 2020
8a53e36
arch: imx6: Fix compile errors in chip.h
masayuki2009 Nov 16, 2020
7e3238e
arch: imx6: Add arm_l2cc_pl310.c to Make.defs
masayuki2009 Nov 16, 2020
16f8535
arch: armv7-a: Fix arm_l2cc_pl310.c with DEBUGASSERT()
masayuki2009 Nov 16, 2020
911d952
boards: sabre-6quad: Enable L2CC for nsh/defconfig
masayuki2009 Nov 16, 2020
8f0f0f0
boards: sabre-6quad: Enable L2CC for smp/defconfig
masayuki2009 Nov 16, 2020
adffd51
arch: armv7-a: Remove unnecessary d-cache operation in arm_cpustart.c
masayuki2009 Nov 16, 2020
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4 changes: 0 additions & 4 deletions arch/arm/src/armv7-a/arm_cpustart.c
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Original file line number Diff line number Diff line change
Expand Up @@ -171,10 +171,6 @@ int up_cpu_start(int cpu)
sched_note_cpu_start(this_task(), cpu);
#endif

/* Make the content of CPU0 L1 cache has been written to coherent L2 */

cp15_clean_dcache(CONFIG_RAM_START, CONFIG_RAM_END - 1);

/* Execute SGI1 */

return arm_cpu_sgi(GIC_IRQ_SGI1, (1 << cpu));
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41 changes: 25 additions & 16 deletions arch/arm/src/armv7-a/arm_l2cc_pl310.c
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-a/chip/arm-l2cc_pl310.c
*
* Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
Expand Down Expand Up @@ -36,7 +36,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/

/****************************************************************************
* Included Files
Expand All @@ -59,13 +59,15 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ***********************************************************/

/* Configuration ************************************************************/

/* Number of ways depends on ARM configuration */

#if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
# define PL310_NWAYS 8
# define PL310_WAY_MASK 0x000000ff
#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY)
# define PL310_NWAYS 16
# define PL310_WAY_MASK 0x0000ffff
#else
Expand Down Expand Up @@ -315,38 +317,45 @@ void arm_l2ccinitialize(void)

/* Make sure that this is a PL310 cache, version r3p2.
*
* REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which is
* r3p2, but the chip that I have actually* reports 0x410000C9 which is some
* later revision.
* REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which
* is r3p2, but the chip that I have actually* reports 0x410000C9 which
* is some later revision.
*/

//DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) == L2CC_IDR_REV_R3P2);
/* DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) ==
* L2CC_IDR_REV_R3P2);
*/

/* Make sure that actual cache configuration agrees with the configured
* cache configuration.
*/


#if defined(CONFIG_ARMV7A_ASSOCIATIVITY_8WAY)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0);
#elif defined(CONFIG_ARMV7A_ASSOCIATIVITY_16WAY)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 1);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == L2CC_ACR_ASS);
#else
# error No associativity selected
#endif

#if defined(CONFIG_ARMV7A_WAYSIZE_16KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_16KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_16KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_32KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_32KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_32KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_64KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_64KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_64KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_128KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_128KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_128KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_256KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_256KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_256KB);
#elif defined(CONFIG_ARMV7A_WAYSIZE_512KB)
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) == L2CC_ACR_WAYSIZE_512KB);
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
L2CC_ACR_WAYSIZE_512KB);
#else
# error No way size selected
#endif
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