Skip to content

arch/z80/src/ez80/ez80_spi.c: Correct oversight in previous commit #467

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
Ouss4 merged 1 commit into from
Mar 7, 2020
Merged

arch/z80/src/ez80/ez80_spi.c: Correct oversight in previous commit #467

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
11 changes: 6 additions & 5 deletions arch/z80/src/ez80/ez80_spi.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -236,7 +236,8 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
outp(EZ80_SPI_BRG_L, brg & 0xff);
outp(EZ80_SPI_BRG_H, (brg >> 8) & 0xff);

g_spi_actual = ((EZ80_SYS_CLK_FREQ + 1) / 2 + brg - 1) / brg;
g_spi_frequency = frequency;
g_spi_actual = ((EZ80_SYS_CLK_FREQ + 1) / 2 + brg - 1) / brg;

finfo("BRG=%lu Actual=%lu\n",
(unsigned long)brg, (unsigned long)g_spi_actual);
Expand Down Expand Up @@ -580,10 +581,10 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
* prior to calling this function. Specifically: GPIOs should have
* been configured for output, and all chip selects disabled.
*
* One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However,
* If multiple devices on on the bus, then multiple chip selects will be
* required. Therefore, all GPIO chip management is deferred to board-
* specific logic.
* One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select.
* However, if multiple devices on on the bus, then multiple chip
* selects will be required. Therefore, all GPIO chip management is
* deferred to board-specific logic.
*
* Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
Expand Down
4 changes: 0 additions & 4 deletions boards/z80/ez80/z20x/src/z20x.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -86,10 +86,6 @@
* Chip select 3 is not used
*/

/****************************************************************************
* Pre-processor Definitions
****************************************************************************/

/* RAM Memory map
*
* 040000 Beginning of RAM
Expand Down