Ensure SFR CKTRIM register correctly set, SAMA5D2/D3 only #8141
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Summary
When using UPLL clock on SAMA5D2 and SAMA5D3 with a crystal which is NOT 12MHz, the CKTRIM SFR register bits must be set correctly to allow the 480MHz clock to run at the correct frequency.
Also found that the SFR bit definitions for this were incorrectly applied to SAMA5D4 but they only apply to SAMA5D2 and SAMA5D3 as best as I can tell.
Impact
None, since these bits had never been set in previous versions of NuttX.
Testing
Custom board with SAMA5D27C-D1G, using 24MHz crystal, and USB host and device connections.