Port to the latest stable Chisel release #33
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Thank you @ekiwi - glad to see your changes use the latest stable release. |
Contributor
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@vegaluisjose @liangfu can you take a look? thanks! |
aasorokiin
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Aug 22, 2021
…pache#33) * Fix Makefile to use Chisel -o instead of top name and .sv instead of .v * fix reset to reset.asBool * fix SyncQueue to deprecated module.io * fix toBools to asBools
tmoreau89
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Sep 9, 2021
* VTA Chisel Wide memory interface.
* Added SyncQueue with tests - Implementation uses sync memory to implement larger queues.
* AXI 64/128/256/512 data bits support by AXIParams->dataBits
A wide implementation of load/store is used when AXI interface data width
is larger than number of bits in a tesor.
Instructions are stored as 64bit tensors to allow 64bit address alignment
* TensorLoad is modified to replace all VME load operations.
Multiple simultaneous requests can be generated. Load is pipelined
and separated from request generation.
* TensorStore -> TensorStoreNarrowVME TensorStoreWideVME. The narrow one is the original one
* TensorLoad -> TensorLoadSimple (original) TensorLoadWideVME TensorStoreNarrowVME
* LoadUop -> LoadUopSimple is the original one. The new one is based on TensorLoad
* Fetch -> FetchVME64 FetchWideVME. Reuse communication part from TensorLoad.
* DPI intreface changed to transfer more than 64bit. svOpenArrayHandle is used. tsim library compilation now requires verilator
* Compute is changed to use TensorLoad style of load uop.
* VME changed to generate/queue/respond to multiple simultaneous load requests
* code formatting fix
* Update to Chisel 3.4.3 PR Port to the latest stable Chisel release (#33)
* Fix Makefile to use Chisel -o instead of top name and .sv instead of .v
* fix reset to reset.asBool
* fix SyncQueue to deprecated module.io
* fix toBools to asBools
* include Verialted.cpp verilated_dpi.cpp directly in module.cc to provide verilator array acces fuctionality and avoid compilation warnings
* fix module io warnings
* comments
* Jenkinsfile ci pipeline fix
* Jenkinsfile ci pipeline fix. only for lint,cpu,i386
* Reenable tsim tests
* style fix
* comments cleanup
* AXI constants commented. Moved write id to VME
* comments cleanup
* comments cleanup
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This PR ports the chisel hardware to use the latest stable release.
It also cleans up any deprecation warnings.