[TIR][Schedule] Relax cache read/write's restriction and fix unexpected behavior #12766
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| vi = T.axis.S(128, i * 16 + j) | ||
| B[vi] = A[vi] + 1.0 | ||
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| for i in T.grid(128): |
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Why do we need to change this testcase? A common practice is not to change the existing test case if possible.
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Thanks, indeed. but if considering a case that R-W-R a same buffer, and we want to cache_read the second R, the 1st R should be ignored. This PR's solution is to specify the 2nd R in consumer_blocks and ignore R if it is not in consumer_blocks. So for this test case, block("B") is ignored. Since the purpose of this case is to cache_read block("C"), the cache block seems to be more reasonable if next to block("C"). Any better solutions is welcomed.
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…ed behavior (apache#12766) [TIR][Schedule] Relax cache read/write's restriction and fix unexpected behavior. Co-authored-by: Min Chen <chen.min@intellif.com>
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Currently, cache read/write requires to be stage pipeline, but it is unnecessary theoretically.
When there is WAR, the target of cache_read could be specified by the consumer_blocks parameter. This also allows cache_write to handle the write after read of the same buffer.
cc @Hzfengsy @junrushao1994 @wrongtest-intellif