[TIR][Schedule] Add cache_inplace primitive to cache opaque buffer #12939
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wrongtest-intellif
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Hzfengsy
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LGTM. Thanks @multiverstack-intellif for adding new primitives!
wrongtest-intellif
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If a block both read and write a buffer, it cannot do cache read/write separately, otherwise dependency breaks. This primitive perform cache read & write together to keep IR correct.
cc @Hzfengsy @wrongtest-intellif