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[Hexagon] Denote DMA cache bypass as experimental feature #13699

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Merged
masahi merged 1 commit into from
Jan 4, 2023
Merged

[Hexagon] Denote DMA cache bypass as experimental feature #13699

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8 changes: 7 additions & 1 deletion src/driver/driver_api.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -53,9 +53,15 @@ TVM_REGISTER_PASS_CONFIG_OPTION("tir.debug_keep_trivial_loop", Bool);
TVM_REGISTER_PASS_CONFIG_OPTION("tir.use_async_copy", Bool);
TVM_REGISTER_PASS_CONFIG_OPTION("tir.merge_async_commit_queue_scope", Bool);
TVM_REGISTER_PASS_CONFIG_OPTION("tir.instrument_lwp", Bool);
TVM_REGISTER_PASS_CONFIG_OPTION("tir.dma_bypass_cache", Bool);
TVM_REGISTER_PASS_CONFIG_OPTION("tir.vtcm_capacity", Integer);

// WARNING: May cause coherency issues resulting data miscompares
// Experimental feature that, when enabled by the runtime, bypasses the cache when using DMA. When
// bypassing the cache TVM must manage cache coherency in software. Software managed cache coherency
// can be tricky e.g. it is yet to be proven out in the Hexagon runtime. Hence the warning above and
// the "experimental" notation for this feature.
TVM_REGISTER_PASS_CONFIG_OPTION("tir.experimental_dma_bypass_cache", Bool);

using tvm::Array;
using tvm::transform::Pass;

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3 changes: 2 additions & 1 deletion src/tir/transforms/lower_async_dma.cc
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Expand Up @@ -211,7 +211,8 @@ namespace transform {
Pass LowerAsyncDMA() {
auto pass_func = [=](PrimFunc f, IRModule m, PassContext ctx) {
auto fptr = f.CopyOnWrite();
bool dma_bypass_cache = ctx->GetConfig<Bool>("tir.dma_bypass_cache", Bool(false)).value();
bool dma_bypass_cache =
ctx->GetConfig<Bool>("tir.experimental_dma_bypass_cache", Bool(false)).value();
fptr->body = AsyncDMALowerer(dma_bypass_cache)(std::move(fptr->body));
return f;
};
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2 changes: 1 addition & 1 deletion tests/python/contrib/test_hexagon/test_async_dma_pipeline.py
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Expand Up @@ -275,7 +275,7 @@ def evaluate(
with tvm.transform.PassContext(
config={
"tir.use_async_copy": use_async_copy,
"tir.dma_bypass_cache": 1,
"tir.experimental_dma_bypass_cache": 1,
"tir.merge_async_commit_queue_scope": merge_async_commit_queue_scope,
}
):
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2 changes: 1 addition & 1 deletion tests/python/contrib/test_hexagon/test_software_pipeline_async.py
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Expand Up @@ -180,7 +180,7 @@ def test_async_software_pipeline(
with tvm.transform.PassContext(
config={
"tir.use_async_copy": 1,
"tir.dma_bypass_cache": 1,
"tir.experimental_dma_bypass_cache": 1,
"tir.merge_async_commit_queue_scope": False,
}
):
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