[LLVM CodeGen] Solve LLVM CodeGen br instruction accept not-i1 type issue

[FrozenGene]

see issue: #2364

LLVM br instruction can only accept i1 type of condition (https://llvm.org/docs/LangRef.html#br-instruction), if the condition type is not i1, we couldn't rewrite to tvm_if_then_else, which is converted to LLVM br instruction. This situation could happen in the situation conv2d + prelu via auto tvm tunning on ARM CPU.

@tqchen please help to review it.
cc: @nttstar

[tqchen]

This is a bit strange, shall we make sure the condition of prelu is bool instead?

[FrozenGene]

Prelu is implemented in select statement, prelu helps us expose this issue. In theory, we can constrtuct other cases using select (condition type is N x i1) to expose this issue.

[FrozenGene]

Supplement of previous comment. LLVM select instruction can accept i1 or vector of i1 (N xi1) type, see: https://llvm.org/docs/LangRef.html#select-instruction But br can only accept i1 type, so this is why I say we can construct using select (N x i1) to expose this issue.

[tqchen]

Thanks, @FrozenGene for the explaination. I have a follow-up PR that is related #2389 The root cause of this error is when if_then_else get vectorized which causes incorrect semantics.