[VERILOG] Generalize Buffer and Tests

tests/verilog/test_buffer_doublebuff.py

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+import tvm
+import numpy as np
+from tvm.addon import verilog
+
+def test_buffer_doublebuff():
+    # Test the tvm_buffer.v module as a double buffer
+    # Window size is 16, buffer size is 32
+    window_width = 16
+    set_size = 8
+
+    # Find file will search root/verilog and root/tests/verilog
+    sess = verilog.session([
+        verilog.find_file("test_buffer_doublebuff.v"),
+        verilog.find_file("tvm_buffer.v")
+    ])
+
+    # Get the handles by their names
+    rst = sess.main.rst
+    write_advance = sess.main.write_advance
+    write_addr = sess.main.write_addr
+    write_valid = sess.main.write_valid
+    write_ready = sess.main.write_ready
+    write_data = sess.main.write_data
+    read_data = sess.main.read_data
+    read_data_valid = sess.main.read_data_valid
+
+    # Simulation input data
+    test_data = np.arange(window_width*set_size).astype('int8')
+
+    # Initial state
+    rst.put_int(1)
+    write_advance.put_int(0)
+    write_addr.put_int(0)
+    write_valid.put_int(0)
+    write_data.put_int(0)
+
+    # De-assert reset
+    sess.yield_until_posedge()
+    rst.put_int(0)
+
+    # Leave the following signals set to true
+    sess.yield_until_posedge()
+    write_valid.put_int(1)
+
+    # Main simulation loop
+    write_idx = 0
+    read_idx = 0
+    while read_idx < len(test_data):
+        # write logic
+        if (write_idx < len(test_data)):
+            write_advance.put_int(0)
+            if (write_ready.get_int()):
+                write_data.put_int(test_data[write_idx])
+                write_addr.put_int(write_idx%window_width)
+                if (write_idx%window_width==window_width-1):
+                    write_advance.put_int(1)
+                write_idx += 1
+        else:
+            write_advance.put_int(0)
+            write_valid.put_int(0)
+
+        # correctness checks
+        if (read_data_valid.get_int()):
+            assert(read_data.get_int()==test_data[read_idx])
+            # print "{} {}".format(read_data.get_int(), test_data[read_idx])
+            read_idx += 1
+
+        # step
+        sess.yield_until_posedge()
+
+
+if __name__ == "__main__":
+    test_buffer_doublebuff()

tests/verilog/test_buffer_doublebuff.v

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+module main();
+
+    // Parameters
+    parameter PER=10;
+
+    // Double buffer parameters
+    parameter DATA_WIDTH = 8;
+    parameter DEPTH = 32;
+    parameter CNTR_WIDTH = 6; // floor(log(32)) + 1
+    parameter RD_WINDOW = 16;
+    parameter RD_ADVANCE = 16;
+    parameter RD_ADDR_WIDTH = 5; // floor(log(16)) + 1
+    parameter WR_WINDOW = 16;
+    parameter WR_ADVANCE = 16;
+    parameter WR_ADDR_WIDTH = 5; // floor(log(16)) + 1
+
+    // Clock & reset
+    reg clk;
+    reg rst;
+
+    // Read port inputs
+    reg read_advance;
+    reg [RD_ADDR_WIDTH-1:0] read_addr;
+    reg read_ready;
+    // Write port outputs
+    reg write_advance;
+    reg [DATA_WIDTH-1:0] write_data;
+    reg [WR_ADDR_WIDTH-1:0] write_addr;
+    reg write_valid;
+
+    // Outputs
+    wire [DATA_WIDTH-1:0] read_data;
+    wire read_valid;
+    wire write_ready;
+    wire [CNTR_WIDTH-1:0] status_counter;
+
+    // Module instantiation
+    tvm_buffer #(
+        .DATA_WIDTH(DATA_WIDTH),
+        .DEPTH(DEPTH),
+        .CNTR_WIDTH(CNTR_WIDTH),
+        .RD_WINDOW(RD_WINDOW),
+        .RD_ADVANCE(RD_ADVANCE),
+        .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+        .WR_WINDOW(WR_WINDOW),
+        .WR_ADVANCE(WR_ADVANCE),
+        .WR_ADDR_WIDTH(WR_ADDR_WIDTH)
+    ) uut (
+        .clk(clk),
+        .rst(rst),
+        .read_advance(read_advance),
+        .read_data(read_data),
+        .read_addr(read_addr),
+        .read_ready(read_ready),
+        .read_valid(read_valid),
+        .write_advance(write_advance),
+        .write_data(write_data),
+        .write_addr(write_addr),
+        .write_ready(write_ready),
+        .write_valid(write_valid),
+        .status_counter(status_counter)
+    );
+
+    // clock generation
+    always begin
+      #(PER/2) clk =~ clk;
+    end
+
+    // read logic
+    always @(posedge clk) begin
+        if (rst) begin
+            read_advance <= 0;
+            read_addr <= 0;
+            read_ready <= 0;
+        end else begin
+            if (read_valid) begin
+                read_ready <= 1;
+            end else begin
+                read_ready <= 0;
+            end
+            if (read_addr%RD_WINDOW==RD_WINDOW-2) begin
+                read_advance <= 1;
+            end else begin
+                read_advance <= 0;
+            end
+            if (read_ready) begin
+                read_addr <= (read_addr+1) % WR_WINDOW;
+            end else begin
+                read_addr <= read_addr % WR_WINDOW;
+            end
+        end
+    end
+
+    // read_data_valid logic
+    reg read_data_valid;
+    always @(posedge clk) begin
+        if (rst)
+            read_data_valid <= 0;
+        else
+            read_data_valid <= read_ready;
+    end
+
+    initial begin
+        // This will allow tvm session to be called every cycle.
+        $tvm_session(clk);
+    end
+endmodule

tests/verilog/test_buffer_fifo.py

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+import tvm
+import numpy as np
+from tvm.addon import verilog
+
+def test_buffer_fifo():
+    # Test the tvm_buffer.v module as a fifo
+
+    # Find file will search root/verilog and root/tests/verilog
+    sess = verilog.session([
+        verilog.find_file("test_buffer_fifo.v"),
+        verilog.find_file("tvm_buffer.v")
+    ])
+
+    # Get the handles by their names
+    rst = sess.main.rst
+    enq = sess.main.enq
+    write_data = sess.main.write_data
+    read_data = sess.main.read_data
+    read_data_valid = sess.main.read_data_valid
+
+    # Simulation input data
+    test_data = np.arange(16).astype('int8')
+
+    # Initial state
+    rst.put_int(1)
+    enq.put_int(0)
+    write_data.put_int(0)
+
+    # De-assert reset
+    sess.yield_until_posedge()
+    rst.put_int(0)
+
+    # Main simulation loop
+    read_idx = 0
+    write_idx = 0
+    while read_idx < len(test_data):
+        # write logic
+        if (write_idx < len(test_data)):
+            enq.put_int(1)
+            write_data.put_int(write_idx)
+            write_idx += 1
+        else:
+            enq.put_int(0)
+        # read logic
+        if (read_data_valid.get_int()):
+            assert(read_data.get_int()==test_data[read_idx])
+            read_idx += 1
+        # step
+        sess.yield_until_posedge()
+
+
+if __name__ == "__main__":
+    test_buffer_fifo()

tests/verilog/test_buffer_fifo.v

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+module main();
+
+    // Parameters
+    parameter PER=10;
+
+    // FIFO parameters
+    parameter DATA_WIDTH = 8;
+    parameter DEPTH = 32;
+    parameter CNTR_WIDTH = 6; // floor(log(32)) + 1
+    parameter RD_WINDOW = 1;
+    parameter RD_ADVANCE = 1;
+    parameter RD_ADDR_WIDTH = 1;
+    parameter WR_WINDOW = 1;
+    parameter WR_ADVANCE = 1;
+    parameter WR_ADDR_WIDTH = 1;
+
+    // Clock & reset
+    reg clk;
+    reg rst;
+
+    // Module inputs
+    reg [DATA_WIDTH-1:0] write_data;
+    // FIFO interface abstraction:
+    // Connect deq to read_advance and read_ready
+    // Connect enq to write_advance and write_valid
+    // Set read_addr and write_addr to 0
+    reg deq;
+    reg enq;
+
+    // Module outputs
+    wire [DATA_WIDTH-1:0] read_data;
+    wire read_valid;
+    wire write_ready;
+    wire [CNTR_WIDTH-1:0] status_counter;
+
+    // Module instantiation
+    tvm_buffer #(
+        .DATA_WIDTH(DATA_WIDTH),
+        .DEPTH(DEPTH),
+        .CNTR_WIDTH(CNTR_WIDTH),
+        .RD_WINDOW(RD_WINDOW),
+        .RD_ADVANCE(RD_ADVANCE),
+        .RD_ADDR_WIDTH(RD_ADDR_WIDTH),
+        .WR_WINDOW(WR_WINDOW),
+        .WR_ADVANCE(WR_ADVANCE),
+        .WR_ADDR_WIDTH(WR_ADDR_WIDTH)
+    ) uut (
+        .clk(clk),
+        .rst(rst),
+        .read_advance(deq),
+        .read_addr({RD_ADDR_WIDTH{1'b0}}),
+        .read_ready(deq),
+        .read_valid(read_valid),
+        .read_data(read_data),
+        .write_advance(enq),
+        .write_addr({WR_ADDR_WIDTH{1'b0}}),
+        .write_ready(write_ready),
+        .write_valid(enq),
+        .write_data(write_data),
+        .status_counter(status_counter)
+    );
+
+    // clock generation
+    always begin
+      #(PER/2) clk =~ clk;
+    end
+
+    // fifo read logic
+    always @(posedge clk) begin
+        if (rst)
+            deq <= 0;
+        else
+            deq <= read_valid;
+    end
+
+    // read_data_valid logic
+    reg read_data_valid;
+    always @(posedge clk) begin
+        if (rst)
+            read_data_valid <= 0;
+        else
+            read_data_valid <= deq;
+    end
+
+    initial begin
+        // This will allow tvm session to be called every cycle.
+        $tvm_session(clk);
+    end
+endmodule