[microTVM] Update support for ARMv7m intrinsic

python/tvm/relay/op/strategy/arm_cpu.py

@@ -127,8 +127,7 @@ def conv2d_strategy_arm_cpu(attrs, inputs, out_type, target):
                 name="conv2d_hwcn.generic",
             )
         elif layout == "NHWC":
-            channels = data.shape[3]
-            if "SMLAD" in isa and (channels % 4) == 0 and kernel_layout == "HWOI":
+            if "SMLAD" in isa and kernel_layout == "HWOI":
                 strategy.add_implementation(
                     wrap_compute_conv2d(topi.arm_cpu.conv2d_direct_simd),
                     wrap_topi_schedule(topi.arm_cpu.schedule_conv2d_direct_simd),

python/tvm/topi/arm_cpu/cortex_m7/conv2d/direct_simd.py

@@ -112,10 +112,14 @@ def conv2d_direct_simd_compute(cfg, data, kernel, strides, padding, dilation, ou
         cfg.reduce_axis(in_channels.value),
     )
 
-    assert in_channels.value % 4 == 0
     owo, owi = cfg.define_split("tile_ow", ow, policy="factors", num_outputs=2)
     cio, cii = cfg.define_split(
-        "tile_ci", ci, policy="factors", num_outputs=2, filter=lambda x: x.size[-1] % 4 == 0
+        "tile_ci",
+        ci,
+        policy="factors",
+        num_outputs=2,
+        # TODO: check case with in_channels.value % 4 != 0 with AutoTVM
+        filter=None if cfg.is_fallback else lambda x: x.size[-1] % 4 == 0,
     )
     coo, coi = cfg.define_split("tile_co", co, policy="factors", num_outputs=2)
 
@@ -134,6 +138,11 @@ def conv2d_direct_simd_compute(cfg, data, kernel, strides, padding, dilation, ou
     cfg.define_knob("auto_unroll_max_step", [0, 2, 4, 8, 16, 32])
     cfg.define_knob("unroll_explicit", [0, 1])
 
+    if cfg.is_fallback:
+        cfg.fallback_split("tile_ow", [-1, out_width.value])
+        cfg.fallback_split("tile_ci", [-1, in_channels.value])
+        cfg.fallback_split("tile_co", [-1, out_channels.value])
+
     return conv