Feature: lint and tooling upgrades

.github/workflows/build-pr.yml

@@ -33,9 +33,9 @@ jobs:
     strategy:
       matrix:
         os:
-          - {id: ubuntu-22.04, name: jammy}
+          - {id: ubuntu-24.04, name: noble}
         arm-compiler:
-          - '12.2.Rel1'
+          - '14.2.Rel1'
         probe:
           - '96b_carbon'
           - 'blackpill-f401cc'
@@ -78,7 +78,7 @@ jobs:
       # Install and setup a suitable Meson + Ninja
       - name: Setup Meson + Ninja
         run: |
-          sudo python3 -m pip install --upgrade pip setuptools wheel
+          sudo apt install -y python3-pip python3-setuptools python3-wheel
           sudo python3 -m pip install meson ninja
         working-directory: ${{ runner.temp }}
 
@@ -125,7 +125,7 @@ jobs:
     strategy:
       matrix:
         os:
-          - windows-2022
+          - windows-2025
       fail-fast: false
 
     # Steps represent a sequence of tasks that will be executed as part of the job
@@ -184,7 +184,7 @@ jobs:
     strategy:
       matrix:
         os:
-          - windows-2022
+          - windows-2025
         sys:
           - {abi: mingw64, env: x86_64, compiler: gcc}
           - {abi: ucrt64, env: ucrt-x86_64, compiler: gcc}
@@ -271,6 +271,7 @@ jobs:
         os:
           - macos-13
           - macos-14
+          - macos-15
           - macos-latest
       fail-fast: false
 
@@ -325,13 +326,14 @@ jobs:
     strategy:
       matrix:
         os:
-          - macos-13
           - macos-14
+          - macos-15
         compiler:
           - gcc@11
           - gcc@12
           - gcc@13
-          - gcc@14 # Don't use 'gcc', the symlink is versioned -- see below
+          - gcc@14
+          - gcc@15 # Don't use 'gcc', the symlink is versioned -- see below
       fail-fast: false
 
     # Steps represent a sequence of tasks that will be executed as part of the job
@@ -384,7 +386,7 @@ jobs:
           meson compile -C build
 
   size-diff:
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
 
     steps:
       # Build a suitable runtime environment
@@ -400,12 +402,12 @@ jobs:
       - name: Setup ARM GCC
         uses: carlosperate/arm-none-eabi-gcc-action@v1
         with:
-          release: '12.2.Rel1'
+          release: '14.2.Rel1'
 
       # Install and setup a suitable Meson + Ninja
       - name: Setup Meson + Ninja
         run: |
-          sudo python3 -m pip install --upgrade pip setuptools wheel
+          sudo apt install -y python3-pip python3-setuptools python3-wheel
           sudo python3 -m pip install meson ninja
         working-directory: ${{ runner.temp }}
 

.pre-commit-config.yaml

@@ -1,8 +1,8 @@
 exclude: '^upgrade/|^scripts/'  # don't run hooks on scripts/ and upgrade/
 
 repos:
-- repo: https://github.com/ssciwr/clang-format-hook
-  rev: v16.0.2
+- repo: https://github.com/pre-commit/mirrors-clang-format
+  rev: v18.1.8
   hooks:
   - id: clang-format
     # entries here override, not extend, upstream's configuration

SECURITY.md

@@ -4,8 +4,10 @@
 
 | Version |     Supported      |
 |---------|--------------------|
+|   2.0.x | :white_check_mark: |
+|  1.10.x | :white_check_mark: |
 |   1.9.x | :white_check_mark: |
-|   1.8.x | :white_check_mark: |
+|   1.8.x | :x:                |
 |<= 1.7.x | :x:                |
 
 Any older version not listed in the above table is also not supported

cross-file/stlink.ini

@@ -19,7 +19,7 @@ endian = 'little'
 
 [project options]
 probe = 'stlink'
-targets = 'cortexm,lpc,nrf,nxp,renesas,sam,stm,ti'
+targets = 'cortexm,lpc,nrf,nxp,sam,stm,ti'
 rtt_support = false
 stlink_swim_nrst_as_uart = false
 bmd_bootloader = false

src/include/align.h

@@ -42,10 +42,10 @@ typedef enum align {
 	ALIGN_64BIT = 3U,
 } align_e;
 
-#define ALIGN_OF(x)     (((x)&3U) == 0 ? ALIGN_32BIT : (((x)&1U) == 0 ? ALIGN_16BIT : ALIGN_8BIT))
+#define ALIGN_OF(x)     (((x) & 3U) == 0 ? ALIGN_32BIT : (((x) & 1U) == 0 ? ALIGN_16BIT : ALIGN_8BIT))
 #define MIN_ALIGN(x, y) MIN(ALIGN_OF(x), ALIGN_OF(y))
 
-#define ALIGN(x, n) (((x) + (n)-1) & ~((n)-1))
+#define ALIGN(x, n) (((x) + (n) - 1) & ~((n) - 1))
 
 #define BMD_ALIGN_DEF(x) _Alignas(x)
 

src/platforms/f072/atomic.c

@@ -164,3 +164,25 @@ uint16_t __atomic_fetch_sub_2(volatile void *atomic_value, uint16_t add_value, i
 bool __atomic_compare_exchange_2(volatile void *atomic_value, void *expected_value, uint16_t new_value, bool weak,
 	int success_model, int failure_model) __attribute__((alias("atomic_compare_exchange_2")));
 /* NOLINTEND(bugprone-reserved-identifier,cert-dcl37-c,cert-dcl51-cpp,readability-identifier-naming) */
+
+/* GCC 14 and newer don't provide __atomic_test_and_set, so we have to here */
+#if __GNUC__ >= 14
+bool atomic_test_and_set(uint8_t *atomic_value, int swap_model)
+{
+	/* Create a model-appropriate sequence barrier to start, and begin a protected block */
+	pre_seq_barrier(swap_model);
+	const uint32_t protect_state = protect_begin(atomic_value);
+
+	/* Read out the current value of the atomic, exchange it with a truthy value */
+	const uint8_t old_value = *atomic_value;
+	*atomic_value = __GCC_ATOMIC_TEST_AND_SET_TRUEVAL;
+
+	/* Finish up with a model-appropriate sequence barrier having ended the protected block */
+	protect_end(atomic_value, protect_state);
+	post_seq_barrier(swap_model);
+	/* Return if the value was already truthy */
+	return old_value != 0U;
+}
+
+bool __atomic_test_and_set(volatile void *atomic_value, int swap_model) __attribute__((alias("atomic_test_and_set")));
+#endif

src/platforms/hosted/windows/ftdi.h

@@ -66,7 +66,8 @@ enum ftdi_module_detach_mode {
 #define DRIVE_OPEN_COLLECTOR 0x9eU
 /* Value Low */
 /* Value HIGH */ /*rate is 12000000/((1+value)*2) */
-#define DIV_VALUE(rate) ((rate) > 6000000U) ? 0U : ((6000000U / (rate)-1U) > 0xffffU) ? 0xffffU : (6000000U / (rate)-1U)
+#define DIV_VALUE(rate) \
+	((rate) > 6000000U) ? 0U : ((6000000U / (rate) - 1U) > 0xffffU) ? 0xffffU : (6000000U / (rate) - 1U)
 
 /* Commands in MPSSE and Host Emulation Mode */
 #define SEND_IMMEDIATE 0x87U

src/platforms/stlinkv3/platform.c

@@ -52,8 +52,8 @@ static uint32_t hw_version;
 #define SCB_CCSIDR_NUMSETS_SHIFT       13U                                    /*!< SCB CCSIDR: NumSets Position */
 #define SCB_CCSIDR_ASSOCIATIVITY_SHIFT 3U                                     /*!< SCB CCSIDR: Associativity Position */
 #define SCB_CCSIDR_ASSOCIATIVITY_MASK  (0x3ffUL << SCB_CCSIDR_ASSOCIATIVITY_SHIFT) /*!< SCB CCSIDR: Associativity Mask */
-#define CCSIDR_WAYS(x)                 (((x)&SCB_CCSIDR_ASSOCIATIVITY_MASK) >> SCB_CCSIDR_ASSOCIATIVITY_SHIFT)
-#define CCSIDR_SETS(x)                 (((x)&SCB_CCSIDR_NUMSETS_MASK) >> SCB_CCSIDR_NUMSETS_SHIFT)
+#define CCSIDR_WAYS(x)                 (((x) & SCB_CCSIDR_ASSOCIATIVITY_MASK) >> SCB_CCSIDR_ASSOCIATIVITY_SHIFT)
+#define CCSIDR_SETS(x)                 (((x) & SCB_CCSIDR_NUMSETS_MASK) >> SCB_CCSIDR_NUMSETS_SHIFT)
 #define SCB_DCISW_SET_SHIFT            5U                               /*!< SCB DCISW: Set Position */
 #define SCB_DCISW_SET_MASK             (0x1ffUL << SCB_DCISW_SET_SHIFT) /*!< SCB DCISW: Set Mask */
 #define SCB_DCISW_WAY_SHIFT            30U                              /*!< SCB DCISW: Way Position */

src/target/adiv5.h

@@ -85,7 +85,7 @@
 #define ADIV5_DP_CTRLSTAT_CDBGRSTREQ   (1U << 26U)
 /* Bits 25:24 - Reserved */
 /* Bits 23:12 - TRNCNT */
-#define ADIV5_DP_CTRLSTAT_TRNCNT(x) (((x)&0xfffU) << 12U)
+#define ADIV5_DP_CTRLSTAT_TRNCNT(x) (((x) & 0xfffU) << 12U)
 /* Bits 11:8 - MASKLANE */
 #define ADIV5_DP_CTRLSTAT_MASKLANE
 /* Bits 7:6 - Reserved in JTAG-DP */
@@ -153,19 +153,19 @@
 /* AP Identification Register (IDR) */
 #define ADIV5_AP_IDR_REVISION_OFFSET 28U
 #define ADIV5_AP_IDR_REVISION_MASK   0xf0000000U
-#define ADIV5_AP_IDR_REVISION(idr)   (((idr)&ADIV5_AP_IDR_REVISION_MASK) >> ADIV5_AP_IDR_REVISION_OFFSET)
+#define ADIV5_AP_IDR_REVISION(idr)   (((idr) & ADIV5_AP_IDR_REVISION_MASK) >> ADIV5_AP_IDR_REVISION_OFFSET)
 #define ADIV5_AP_IDR_DESIGNER_OFFSET 17U
 #define ADIV5_AP_IDR_DESIGNER_MASK   0x0ffe0000U
-#define ADIV5_AP_IDR_DESIGNER(idr)   (((idr)&ADIV5_AP_IDR_DESIGNER_MASK) >> ADIV5_AP_IDR_DESIGNER_OFFSET)
+#define ADIV5_AP_IDR_DESIGNER(idr)   (((idr) & ADIV5_AP_IDR_DESIGNER_MASK) >> ADIV5_AP_IDR_DESIGNER_OFFSET)
 #define ADIV5_AP_IDR_CLASS_OFFSET    13U
 #define ADIV5_AP_IDR_CLASS_MASK      0x0001e000U
-#define ADIV5_AP_IDR_CLASS(idr)      (((idr)&ADIV5_AP_IDR_CLASS_MASK) >> ADIV5_AP_IDR_CLASS_OFFSET)
+#define ADIV5_AP_IDR_CLASS(idr)      (((idr) & ADIV5_AP_IDR_CLASS_MASK) >> ADIV5_AP_IDR_CLASS_OFFSET)
 #define ADIV5_AP_IDR_VARIANT_OFFSET  4U
 #define ADIV5_AP_IDR_VARIANT_MASK    0x000000f0U
-#define ADIV5_AP_IDR_VARIANT(idr)    (((idr)&ADIV5_AP_IDR_VARIANT_MASK) >> ADIV5_AP_IDR_VARIANT_OFFSET)
+#define ADIV5_AP_IDR_VARIANT(idr)    (((idr) & ADIV5_AP_IDR_VARIANT_MASK) >> ADIV5_AP_IDR_VARIANT_OFFSET)
 #define ADIV5_AP_IDR_TYPE_OFFSET     0U
 #define ADIV5_AP_IDR_TYPE_MASK       0x0000000fU
-#define ADIV5_AP_IDR_TYPE(idr)       ((idr)&ADIV5_AP_IDR_TYPE_MASK)
+#define ADIV5_AP_IDR_TYPE(idr)       ((idr) & ADIV5_AP_IDR_TYPE_MASK)
 
 #define ADIV5_AP_IDR_CLASS_JTAG 0U
 #define ADIV5_AP_IDR_CLASS_COM  1U

src/target/cortex_internal.h

@@ -44,7 +44,7 @@
 #define CORTEX_CTR_ICACHE_LINE_MASK        0xfU
 #define CORTEX_CTR_DCACHE_LINE_SHIFT       16U
 #define CORTEX_CTR_DCACHE_LINE_MASK        0xfU
-#define CORTEX_CTR_ICACHE_LINE(cache_type) (1U << ((cache_type)&CORTEX_CTR_ICACHE_LINE_MASK))
+#define CORTEX_CTR_ICACHE_LINE(cache_type) (1U << ((cache_type) & CORTEX_CTR_ICACHE_LINE_MASK))
 #define CORTEX_CTR_DCACHE_LINE(cache_type) \
 	(1U << (((cache_type) >> CORTEX_CTR_DCACHE_LINE_SHIFT) & CORTEX_CTR_DCACHE_LINE_MASK))
 

src/target/cortexar.c

@@ -249,7 +249,7 @@ static const uint16_t cortexar_spsr_encodings[5] = {
 	(((opc1) << 21U) | ((crn) << 16U) | ((rt) << 12U) | ((coproc) << 8U) | ((opc2) << 5U) | (crm))
 /* Packs a CRn and CRm value for the coprocessor IO routines below to unpack */
 #define ENCODE_CP_REG(n, m, opc1, opc2) \
-	((((n)&0xfU) << 4U) | ((m)&0xfU) | (((opc1)&0x7U) << 8U) | (((opc2)&0x7U) << 12U))
+	((((n) & 0xfU) << 4U) | ((m) & 0xfU) | (((opc1) & 0x7U) << 8U) | (((opc2) & 0x7U) << 12U))
 
 /*
  * Instruction encodings for coprocessor load/store

src/target/flashstub/efm32.c

@@ -42,8 +42,8 @@
 #define EFM32_MSC_STATUS_WDATAREADY  (1U << 3U)
 #define EFM32_MSC_STATUS_WORDTIMEOUT (1U << 4U)
 
-void __attribute__((naked))
-efm32_flash_write_stub(const uint32_t *const dest, const uint32_t *const src, uint32_t size, const uint32_t msc_addr)
+void __attribute__((naked)) efm32_flash_write_stub(
+	const uint32_t *const dest, const uint32_t *const src, uint32_t size, const uint32_t msc_addr)
 {
 	const uintptr_t msc = msc_addr;
 	EFM32_MSC_LOCK(msc) = EFM32_MSC_LOCK_LOCKKEY;

src/target/flashstub/lmi.c

@@ -31,8 +31,8 @@
 #define LMI_FLASH_FMC_COMT   (1U << 3U)
 #define LMI_FLASH_FMC_WRKEY  0xa4420000U
 
-void __attribute__((naked))
-stm32f1_flash_write_stub(const uint32_t *const dest, const uint32_t *const src, const uint32_t size)
+void __attribute__((naked)) stm32f1_flash_write_stub(
+	const uint32_t *const dest, const uint32_t *const src, const uint32_t size)
 {
 	for (uint32_t i = 0; i < (size / 4U); ++i) {
 		LMI_FLASH_FMA = (uintptr_t)(dest + i);

src/target/flashstub/rp.c

@@ -149,8 +149,8 @@ static void rp_spi_write(const uint32_t address, const uint8_t *const src, const
 	rp_spi_flash_deselect();
 }
 
-static void __attribute__((used, section(".entry")))
-rp_flash_write(const uint32_t dest, const uint8_t *const src, const size_t length, const uint32_t page_size)
+static void __attribute__((used, section(".entry"))) rp_flash_write(
+	const uint32_t dest, const uint8_t *const src, const size_t length, const uint32_t page_size)
 {
 	for (size_t offset = 0; offset < length; offset += page_size) {
 		/* Try to write-enable the Flash */

src/target/imxrt.c

@@ -155,15 +155,15 @@
 #define IMXRT_FLEXSPI1_LUT_CTRL_UNLOCK            0x00000002U
 #define IMXRT_FLEXSPI1_CTRL1_CAS_MASK             0x00007800U
 #define IMXRT_FLEXSPI1_CTRL1_CAS_SHIFT            11U
-#define IMXRT_FLEXSPI1_PRG_LENGTH(x)              ((x)&0x0000ffffU)
-#define IMXRT_FLEXSPI1_PRG_SEQ_INDEX(x)           (((x)&0xfU) << 16U)
+#define IMXRT_FLEXSPI1_PRG_LENGTH(x)              ((x) & 0x0000ffffU)
+#define IMXRT_FLEXSPI1_PRG_SEQ_INDEX(x)           (((x) & 0xfU) << 16U)
 #define IMXRT_FLEXSPI1_PRG_RUN                    0x00000001U
 #define IMXRT_FLEXSPI1_PRG_FIFO_CTRL_CLR          0x00000001U
 #define IMXRT_FLEXSPI1_PRG_FIFO_CTRL_WATERMARK(x) ((((((x) + 7U) >> 3U) - 1U) & 0xfU) << 2U)
 #define IMXRT_FLEXSPI1_PRG_WRITE_FIFO_STATUS_FILL 0x000000ffU
-#define IMXRT_FLEXSI_SLOT_OFFSET(x)               ((x)*16U)
+#define IMXRT_FLEXSI_SLOT_OFFSET(x)               ((x) * 16U)
 
-#define IMXRT_FLEXSPI_LUT_OPCODE(x)   (((x)&0x3fU) << 2U)
+#define IMXRT_FLEXSPI_LUT_OPCODE(x)   (((x) & 0x3fU) << 2U)
 #define IMXRT_FLEXSPI_LUT_MODE_SERIAL 0x0U
 #define IMXRT_FLEXSPI_LUT_MODE_DUAL   0x1U
 #define IMXRT_FLEXSPI_LUT_MODE_QUAD   0x2U

src/target/lpc43xx.c

@@ -189,7 +189,7 @@
 #define LPC43x0_SPIFI_MCMD (LPC43x0_SPIFI_BASE + 0x018U)
 #define LPC43x0_SPIFI_STAT (LPC43x0_SPIFI_BASE + 0x01cU)
 
-#define LPC43x0_SPIFI_DATA_LENGTH(x)       ((x)&0x00003fffU)
+#define LPC43x0_SPIFI_DATA_LENGTH(x)       ((x) & 0x00003fffU)
 #define LPC43x0_SPIFI_DATA_SHIFT           15U
 #define LPC43x0_SPIFI_DATA_IN              (0U << 15U)
 #define LPC43x0_SPIFI_DATA_OUT             (1U << 15U)

src/target/rp2040.c

@@ -110,15 +110,15 @@
 #define RP_SSI_CTRL0_TMOD_EEPROM               (3U << 8U)
 #define RP_SSI_CTRL0_DATA_BIT_MASK             0x001f0000U
 #define RP_SSI_CTRL0_DATA_BIT_SHIFT            16U
-#define RP_SSI_CTRL0_DATA_BITS(x)              (((x)-1U) << RP_SSI_CTRL0_DATA_BIT_SHIFT)
+#define RP_SSI_CTRL0_DATA_BITS(x)              (((x) - 1U) << RP_SSI_CTRL0_DATA_BIT_SHIFT)
 #define RP_SSI_CTRL0_MASK                      (RP_SSI_CTRL0_FRF_MASK | RP_SSI_CTRL0_TMOD_MASK | RP_SSI_CTRL0_DATA_BIT_MASK)
 #define RP_SSI_ENABLE_SSI                      (1U << 0U)
 #define RP_SSI_XIP_SPI_CTRL0_FORMAT_STD_SPI    (0U << 0U)
 #define RP_SSI_XIP_SPI_CTRL0_FORMAT_SPLIT      (1U << 0U)
 #define RP_SSI_XIP_SPI_CTRL0_FORMAT_FRF        (2U << 0U)
-#define RP_SSI_XIP_SPI_CTRL0_ADDRESS_LENGTH(x) (((x)*2U) << 2U)
+#define RP_SSI_XIP_SPI_CTRL0_ADDRESS_LENGTH(x) (((x) * 2U) << 2U)
 #define RP_SSI_XIP_SPI_CTRL0_INSTR_LENGTH_8b   (2U << 8U)
-#define RP_SSI_XIP_SPI_CTRL0_WAIT_CYCLES(x)    (((x)*8U) << 11U)
+#define RP_SSI_XIP_SPI_CTRL0_WAIT_CYCLES(x)    (((x) * 8U) << 11U)
 #define RP_SSI_XIP_SPI_CTRL0_XIP_CMD_SHIFT     24U
 #define RP_SSI_XIP_SPI_CTRL0_XIP_CMD(x)        ((x) << RP_SSI_XIP_SPI_CTRL0_XIP_CMD_SHIFT)
 #define RP_SSI_XIP_SPI_CTRL0_TRANS_1C1A        (0U << 0U)

src/target/samd.c

@@ -104,7 +104,7 @@ const command_s samd_cmd_list[] = {
 #define SAMD_NVM_USER_ROW_LOW  0x00804000U
 #define SAMD_NVM_USER_ROW_HIGH 0x00804004U
 #define SAMD_NVM_CALIBRATION   0x00806020U
-#define SAMD_NVM_SERIAL(n)     (0x0080a00cU + (0x30U * (((n) + 3U) / 4U)) + ((n)*4U))
+#define SAMD_NVM_SERIAL(n)     (0x0080a00cU + (0x30U * (((n) + 3U) / 4U)) + ((n) * 4U))
 
 /* -------------------------------------------------------------------------- */
 /* Device Service Unit (DSU) Registers */

src/target/spi.h

@@ -41,7 +41,7 @@
 #include "spi_types.h"
 
 #define SPI_FLASH_OPCODE_MASK      0x00ffU
-#define SPI_FLASH_OPCODE(x)        ((x)&SPI_FLASH_OPCODE_MASK)
+#define SPI_FLASH_OPCODE(x)        ((x) & SPI_FLASH_OPCODE_MASK)
 #define SPI_FLASH_DUMMY_MASK       0x0700U
 #define SPI_FLASH_DUMMY_SHIFT      8U
 #define SPI_FLASH_DUMMY_LEN(x)     (((x) << SPI_FLASH_DUMMY_SHIFT) & SPI_FLASH_DUMMY_MASK)

src/target/stm32h5.c

@@ -100,7 +100,7 @@
 #define STM32H5_FLASH_CTRL_SECTOR_ERASE (1U << 2U)
 #define STM32H5_FLASH_CTRL_BANK_ERASE   (1U << 3U)
 #define STM32H5_FLASH_CTRL_START        (1U << 5U)
-#define STM32H5_FLASH_CTRL_SECTOR(x)    (((x)&0x7fU) << 6U)
+#define STM32H5_FLASH_CTRL_SECTOR(x)    (((x) & 0x7fU) << 6U)
 #define STM32H5_FLASH_CTRL_MASS_ERASE   (1U << 15U)
 #define STM32H5_FLASH_CTRL_BANK1        (0U << 31U)
 #define STM32H5_FLASH_CTRL_BANK2        (1U << 31U)