CL/aarch64: implement the wasm SIMD pseudo-max/min and FP-rounding in… #2312
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Looks good with better fmin_pseudo/ fmax_pseudo instruction descriptions (maybe even a note at lower_inst.rs implementation?)
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…structions This patch implements, for aarch64, the following wasm SIMD extensions Floating-point rounding instructions WebAssembly/simd#232 Pseudo-Minimum and Pseudo-Maximum instructions WebAssembly/simd#122 The changes are straightforward: * `build.rs`: the relevant tests have been enabled * `cranelift/codegen/meta/src/shared/instructions.rs`: new CLIF instructions `fmin_pseudo` and `fmax_pseudo`. The wasm rounding instructions do not need any new CLIF instructions. * `cranelift/wasm/src/code_translator.rs`: translation into CLIF; this is pretty much the same as any other unary or binary vector instruction (for the rounding and the pmin/max respectively) * `cranelift/codegen/src/isa/aarch64/lower_inst.rs`: - `fmin_pseudo` and `fmax_pseudo` are converted into a two instruction sequence, `fcmpgt` followed by `bsl` - the CLIF rounding instructions are converted to a suitable vector `frint{n,z,p,m}` instruction. * `cranelift/codegen/src/isa/aarch64/inst/mod.rs`: minor extension of `pub enum VecMisc2` to handle the rounding operations. And corresponding `emit` cases.
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bjorn3
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It was added in bytecodealliance#2312
bjorn3
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It was added in bytecodealliance#2312
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…structions
This patch implements, for aarch64, the following wasm SIMD extensions
Floating-point rounding instructions
WebAssembly/simd#232
Pseudo-Minimum and Pseudo-Maximum instructions
WebAssembly/simd#122
The changes are straightforward:
build.rs: the relevant tests have been enabledcranelift/codegen/meta/src/shared/instructions.rs: new CLIF instructionsfmin_pseudoandfmax_pseudo. The wasm rounding instructions do not needany new CLIF instructions.
cranelift/wasm/src/code_translator.rs: translation into CLIF; this ispretty much the same as any other unary or binary vector instruction (for
the rounding and the pmin/max respectively)
cranelift/codegen/src/isa/aarch64/lower_inst.rs:fmin_pseudoandfmax_pseudoare converted into a two instructionsequence,
fcmpgtfollowed bybslfrint{n,z,p,m}instruction.cranelift/codegen/src/isa/aarch64/inst/mod.rs: minor extension ofpub enum VecMisc2to handle the rounding operations. And correspondingemitcases.