Convert fma, valltrue & vanytrue to ISLE (AArch64)#4608
Convert fma, valltrue & vanytrue to ISLE (AArch64)#4608cfallin merged 2 commits intobytecodealliance:mainfrom
fma, valltrue & vanytrue to ISLE (AArch64)#4608Conversation
Ported the existing implementations of the following opcodes to ISLE on
AArch64:
- `fma`
- Introduced missing support for `fma` on vector values, as per the
docs.
- `valltrue`
- `vanytrue`
Also fixed `fcmp` on scalar values in the interpreter, and enabled
interpreter tests in `simd-fma.clif`.
This introduces the `FMLA` machine instruction.
Copyright (c) 2022 Arm Limited
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| @@ -1,5 +1,7 @@ | |||
| test interpret | |||
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fma is somewhat broken in the interpreter for the x86_64-pc-windows-gnu target (see #4517 for more details). We have a smaller subset of fma tests for the interpreter in a separate file.
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Although it looks like we don't have those problematic inputs in this test file, so the tests will probably pass.
afonso360
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The interpreter changes look good to me!
cfallin
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Thanks! This overall looks good. I have some comments/thoughts on the "in-place" / conditional-mod-operand aspect of VecRRR, but for merging this I think just some more comments will do, and we can clean up the (pre-existing) issue in a followup.
| alu_op, rd, rn, rm, .. | ||
| } => { | ||
| if alu_op == VecALUOp::Bsl { | ||
| if alu_op == VecALUOp::Bsl || alu_op == VecALUOp::Fmla { |
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Hmm, I'm not too happy about the conditional-mod here, but it's pre-existing, so I won't ask you to do anything in this PR. But noting it regardless: it would be better to split the case out to a new enum arm (VecRRRMod?) and then make the sub-opcode enum separate (VecALUOp / VecALUModOp maybe?) for more safety at the type level. (If you want to tackle that in a followup PR, I'd be happy to review!)
Copyright (c) 2022 Arm Limited
Separates the following opcodes for AArch64 into a separate `VecALUModOp` enum, which is emitted via the `VecRRRMod` instruction. This separates vector ALU instructions which modify a register from instructions which write to a new register: - `Bsl` - `Fmla` Addresses [a discussion](bytecodealliance#4608 (comment)) in bytecodealliance#4608. Copyright (c) 2022 Arm Limited
Separates the following opcodes for AArch64 into a separate `VecALUModOp` enum, which is emitted via the `VecRRRMod` instruction. This separates vector ALU instructions which modify a register from instructions which write to a new register: - `Bsl` - `Fmla` Addresses [a discussion](#4608 (comment)) in #4608. Copyright (c) 2022 Arm Limited
3 participants
Ported the existing implementations of the following opcodes to ISLE on
AArch64:
fmafmaon vector values, as per thedocs.
valltruevanytrueAlso fixed
fcmpon scalar values in the interpreter, and enabledinterpreter tests in
simd-fma.clif.This introduces the
FMLAmachine instruction.Copyright (c) 2022 Arm Limited