Skip to content

riscv64: Ignore extends for fcmp #7151

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
cfallin merged 1 commit into from
Oct 4, 2023
Merged

riscv64: Ignore extends for fcmp #7151

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 3 additions & 2 deletions cranelift/codegen/src/isa/riscv64/inst.isle
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2148,9 +2148,10 @@
(rule 1 (val_already_extended (uextend _)) $true)
(rule 1 (val_already_extended (sextend _)) $true)

;; The result of `icmp` is zero or one, meaning that it's already sign extended
;; to the full register width.
;; The result of `icmp`/`fcmp` is zero or one, meaning that it's already sign
;; extended to the full register width.
(rule 1 (val_already_extended (icmp _ _ _)) $true)
(rule 1 (val_already_extended (fcmp _ _ _)) $true)

(type ExtendOp
(enum
Expand Down
18 changes: 18 additions & 0 deletions cranelift/filetests/filetests/isa/riscv64/extend.clif
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -258,3 +258,21 @@ block0(v0: i8, v1: i64):
; add a0, a0, a1
; ret


function %extend_fcmp(f64, f64) -> i64 {
block0(v0: f64, v1: f64):
v3 = fcmp.f64 lt v0, v1
v4 = sextend.i64 v3
return v4
}

; VCode:
; block0:
; flt.d a0,fa0,fa1
; ret
;
; Disassembled:
; block0: ; offset 0x0
; flt.d a0, fa0, fa1
; ret