x64: Add {u,s}mulhi.i8 instruction support#7866
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alexcrichton merged 1 commit intobytecodealliance:mainfrom Feb 3, 2024
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x64: Add {u,s}mulhi.i8 instruction support#7866alexcrichton merged 1 commit intobytecodealliance:mainfrom
{u,s}mulhi.i8 instruction support#7866alexcrichton merged 1 commit intobytecodealliance:mainfrom
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This commit is inspired after reading over some code from bytecodealliance#7865 and bytecodealliance#7866. The goal of this commit was to refactor scalar multiplication-related instructions in the x64 backend to more closely align with their native instructions. Changes include: * The `MulHi` instruction is renamed to `Mul`. This represents either `mul` or `imul` producing a doublewide result. * A `Mul8` instruction was added to correspond to `Mul` for the 8-bit variants that produce a doublewide result in the `AX` register rather than the other instructions which split between `RAX` and `RDX`. * The `UMulLo` instruction was removed as now it's covered by `Mul` * The `AluRmiROpcode::Mul` opcode was removed in favor of new `IMul` and `IMulImm` instructions. Register allocation and emission already had special cases for `Mul` which felt better as standalone instructions rather than putting in an existing variant. Lowerings using `imul` are not affected in general but the `IMulImm` instruction has different register allocation behavior than before which allows the destination to have a different register than the first operand. The `umulhi` and `smulhi` instructions are also reimplemented with their 8-bit variants instead of extension-plus-16-bit variants.
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* x64: Refactor multiplication instructions This commit is inspired after reading over some code from #7865 and #7866. The goal of this commit was to refactor scalar multiplication-related instructions in the x64 backend to more closely align with their native instructions. Changes include: * The `MulHi` instruction is renamed to `Mul`. This represents either `mul` or `imul` producing a doublewide result. * A `Mul8` instruction was added to correspond to `Mul` for the 8-bit variants that produce a doublewide result in the `AX` register rather than the other instructions which split between `RAX` and `RDX`. * The `UMulLo` instruction was removed as now it's covered by `Mul` * The `AluRmiROpcode::Mul` opcode was removed in favor of new `IMul` and `IMulImm` instructions. Register allocation and emission already had special cases for `Mul` which felt better as standalone instructions rather than putting in an existing variant. Lowerings using `imul` are not affected in general but the `IMulImm` instruction has different register allocation behavior than before which allows the destination to have a different register than the first operand. The `umulhi` and `smulhi` instructions are also reimplemented with their 8-bit variants instead of extension-plus-16-bit variants. * Remove outdated emit tests These are all covered by the filetests framework now too. * Fix Winch build
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👋 Hey,
This PR adds support for
smulhi.i8andumulhi.i8to the x64 backend.Closes #5468
Closes #7865