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Chapter 1 Digital Signals And Systems

0. 0. Digital Signals and Systems
1. 1. 1.1 Should Software Engineers Worry About Hardware?
2. 2. 1.2 Non-Digital Signal
3. 3. 1.3 Digital Signals
4. 4. 1.4 Conversion Systems
5. 5. 1.5 Representation of Digital Signals
6. 6. 1.6 Types of Digital Signals
   • 7. 7. 1.6.1 Edges
   • 8. 8. 1.6.2 Pulses
   • 9. 9. 1.6.3 Non-Periodic Pulse Trains
   • 10. 10. 1.6.4 Periodic Pulse Trains
   • 11. 11. 1.6.5 Pulse-Width Modulation
7. 12. 1.7 Unit Prefixes
8. 13. 1.8 What's Next?
9. 14. Problems

Chapter 2: Numbering Systems

1. 1. Unsigned Binary Counting
2. 2. Binary Terminology
3. 3. Unsigned Binary to Decimal Conversion
4. 4. Decimal to Unsigned Binary Conversion
5. 5. Binary Representation of Analog Values
6. 6. Sampling Theory
7. 7. Hexadecimal Representation
8. 8. Binary Coded Decimal
9. 9. Gray Codes
10. 10. What's Next?
11. 11. Problems

Chapter 3: Binary Math and Signed Representations

1. 3.1 Binary Addition
2. 3.2 Binary Subtraction
3. 3.3 Binary Complements
   • 3.3.1 One's Complement
   • 3.3.2 Two's Complement
   • 3.3.3 Most Significant Bit as a Sign Indicator
   • 3.3.4 Signed Magnitude
   • 3.3.5 MSB and Number of Bits
   • 3.3.6 Issues Surrounding the Conversion of Binary Numbers. 52
   • 3.3.7 Minimums and Maximums
4. 3.4 Floating Point Binary
5. 3.5 Hexadecimal Addition
6. 3.6 BCD Addition
7. 3.7 Multiplication and Division by Powers of Two
8. 3.8 Easy Decimal to Binary Conversion Trick
9. 3.9 Arithmetic Overflow
10. 3.10 What's Next?
11. Problems

Chapter 4: Logic Functions and Gates

1. 4.1 Logic Gate Basics
2. 4.1.1 NOT Gate
3. 4.1.2 AND Gate
4. 4.1.3 OR Gate
5. 4.1.4 Exclusive-OR (XOR) Gate
6. 4.2 Truth Tables
7. 4.3 Timing Diagrams for Gates
8. 4.4 Combinational Logic
9. 4.5 Truth Tables for Combinational Logic
10. 4.6 What's Next?
11. Problems

Chapter 5: Boolean Algebra

1. 5.1 Need for Boolean Expressions
2. 5.2 Symbols of Boolean Algebra
3. 5.3 Boolean Expressions of Combinational Logic
4. 5.4 Laws of Boolean Algebra
5. 5.5 Rules of Boolean Algebra
   • 6. 5.5.1 NOT Rule
   • 7. 5.5.2 OR Rules
   • 8. 5.5.3 AND Rules
   • 9. 5.5.4 XOR Rules
   • 10. 5.5.5 Derivation of Other Rules
6. 5.6 Simplification
7. 5.7 DeMorgan's Theorem
8. 5.8 What's Next?
9. Problems

Chapter 6: Standard Boolean Expression Formats

1. 1. Sum-of-Products
2. 2. Converting an SOP Expression to a Truth Table
3. 3. Converting a Truth Table to an SOP Expression
4. 4. Product-of-Sums
5. 5. Converting POS to Truth Table
6. 6. Converting a Truth Table to a POS Expression
7. 7. NAND-NAND Logic
8. 8. What's Next?

Chapter 7: KarnaughMaps

1. 1. The Karnaugh Map
2. 2. Using Karnaugh Maps
3. 3. "Don't Care" Conditions in a Karnaugh Map
4. 4. What's Next?

Chapter 8: Combinational Logic Applications

1. 1. Adders
2. 2. Seven-Segmented Displays
3. 3. Active-Low Signals
4. 4. Decoders
5. 5. Multiplexers
6. 6. Demultiplexers
7. 7. Integrated Circuits
8. 8. What is next?

Chapter 9: Binary Operation Applications

1. 1. Bitwise Operations
2. 2. Clearing/Masking Bits
3. 3. Setting Bits
4. 4. Toggling Bits
5. 5. Comparing Bits with XOR
6. 6. Parity
7. 7. Checksum
8. 8. Cyclic Redundancy Check
9. 9. CRC Process
10. 10. CRC Implementation
11. 11. Hamming Code

Chapter 10: Memory Cells

1. 10.1 New Truth Table Symbols
   • 2. 10.1.1 Edges/Transitions
   • 3. 10.1.2 Previously Stored Values
   • 4. 10.1.3 Undefined Values
2. 10.2 The S-R Latch
3. 10.3 The D Latch
4. 10.4 Divide-By-Two Circuit
5. 10.5 Counter
6. 10.6 Parallel Data Output

Chapter 11: State Machines

1. 11.1 Introduction to State Machines
   • 2. 11.1.1 States
   • 3. 11.1.2 State Diagrams
   • 4. 11.1.3 Errors in State Diagrams
   • 5. 11.1.4 Basic Circuit Organization
2. 11.2 State Machine Design Process
3. 11.3 Another State Machine Design: Pattern Detection
4. 11.4 Mealy Versus Moore State Machines

Chapter 12: Memory Organization

1. 1. 12.1 Early Memory
2. 2. 12.2 Organization of Memory Device
3. 3. 12.3 Interfacing Memory to a Processor
   • 4. 4. 12.3.1 Buses
   • 5. 5. 12.3.2 Memory Maps
   • 6. 6. 12.3.3 Address Decoding
   • 7. 7. 12.3.4 Chip Select Hardware
4. 8. 12.4 Memory Mapped Input/Output
5. 9. 12.5 Memory Terminology
   • 10. 10. 12.5.1 Random Access Memory
   • 11. 11. 12.5.2 Read Only Memory
   • 12. 12. 12.5.3 Static RAM versus Dynamic RAM
   • 13. 13. 12.5.4 Types of DRAM and Their Timing
   • 14. 14. 12.5.5 Asynchronous versus Synchronous Memory Interfacing
6. 15. 12.6 What's Next?

Chapter 13: Memory Hierarchy

1. 1. 13.1 Characteristics of the Memory Hierarchy
2. 2. 13.2 Physical Characteristics of a Hard Drive
   • 3. 3. 13.2.1 Hard Drive Read/Write Head
   • 4. 4. 13.2.2 Data Encoding
   • 5. 5. 13.2.3 Hard Drive Access Time
   • 6. 6. 13.2.4 Self-Monitoring, Analysis & Reporting Technology System
3. 7. 13.3 Organization of Data on a Hard Drive
4. 8. 13.4 Cache RAM
   • 9. 9. 13.4.1 Cache Organization
   • 10. 10. 13.4.2 Dividing Memory into Blocks
   • 11. 11. 13.4.3 Cache Operation
   • 12. 12. 13.4.4 Cache Characteristics
   • 13. 13. 13.4.5 Cache Mapping Functions
5. 14. 13.5 Registers
6. 15. 13.6 What's Next?