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0. Introduction Inside The Machine

0. Introduction

1. Basic Computing Concepts

1. 1. The Calculator Model of Computing
2. 2. The File-Clerk Model of Computing
   • The Stored-Program Computer
   • Refining the File-Clerk Model
3. 3. The Register File
4. 4. RAM: When Registers Alone Won’t Cut It
   • The File-Clerk Model Revisited and Expanded
   • An Example: Adding Two Numbers
5. 5. A Closer Look at the Code Stream: The Program
   • General Instruction Types
   • Arithmetic Instructions
   • Memory-access instructions
   • The DLW-1’s Basic Architecture and Arithmetic Instruction Format
   • The DLW-1's Arithmetic Instructions Format
   • The DLW-1's Memory Instruction Format
   • An example DLW-1 Program
6. 6. A Closer Look at Memory Accesses: Register vs. Immediate
   • Immediate Values
   • Register-Relative Addressing

2. The Mechanics Of Program Execution

1. 1. Opcodes and Machine Language
   • Machine Language on the DLW-1
   • Binary Encoding of Arithmetic Instructions
   • Binary Encoding of Memory Access Instructions
   • The Load Instruction
   • The store instruction
   • Translating an Example Program into Machine Language
2. 2. The Programming Model and the ISA
   • The Programming Model
   • The Instruction Register and Program Counter
   • The Instruction Fetch: Loading the Instruction Register
   • Running a Simple Program: The Fetch-Execute Loop
3. 3. The Clock
4. 4. Branch Instructions
   • Unconditional Branch
   • Conditional Branch
   • Branch Instructions and the Fetch-Execute Loop
   • The Branch Instruction as a Special Type of Load
   • Branch Instructions and Labels
5. 5. Excursus: Booting Up

3. Pipelined Execution

1. 1. The Lifecycle of an Instruction
2. 2. Basic Instruction Flow
3. 3. Pipelining Explained
4. 4. Applying the Analogy
   • A Non-Pipelined Processor
   • A Pipelined Processor
   • Shrink the clock
   • Shrinking Program Execution Time
   • The Speedup from Pipelining
   • Program Execution Time and Completion Rate
   • The Relationship Between Completion Rate and Program Execution Time
   • Instruction Throughput and Pipeline Stalls
   • Instruction Throughput
   • Maximum theorical instruction throughput
   • Average instruction thoughput
   • Pipeline Stalls
   • Instruction Latency and Pipeline Stalls
   • Limits to Pipelining
   • Clock Period and Completion Rate
   • The Cost of Pipelining

4. Super Escalar Execution

0. 0. Super Escalar Execution - Intro
1. 1. Superscalar Computing and IPC (Instruction Per Cycle)
2. 2. Expanding Superscalar Processing with Execution Units
   • 3. 3. Basic Number Formats and Computer Arithmetic
   • 4. 4. Arithmetic Logic Units
   • 5. 5. Memory-Access Units
3. 6. Microarchitecture and the ISA
   • 7. 7. A Brief History of the ISA
   • 8. 8. Moving Complexity from Hardware to Software
4. 9. Challenges to Pipelining and Superscalar Design
   • 10. 10. Data Hazards
   • 11. 11. Structural Hazards
   • 12. 12. The Register File
   • 13. 13. Control Hazards

5. The Intel Pentium And Pentium Pro

1. 1. The Original Pentium
   • 2. 2. Caches
   • 3. 3. The Pentium’s Pipeline
   • 4. 4. The Branch Unit and Branch Prediction
   • 5. 5. The Pentium’s Back End
   • 6. 6. The Integer ALUs
   • 7. 7. The Floating-Point ALU
   • 8. 8. x86 Overhead on the Pentium
   • 9. 9. Summary: The Pentium in Historical Context
2. 10. The Intel P6 Microarchitecture: The Pentium Pro
   • 11. 11. Decoupling the Front End from the Back End
   • 12. 12. The Issue Phase
   • 13. 13. The Completion Phase
   • 14. 14. The P6’s Issue Phase: The Reservation Station
   • 15. 15. The P6’s Completion Phase: The Reorder Buffer
   • 16. 16. The Instruction Window
   • 17. 17. The P6 Pipeline
   • 18. 18. BTB access and instruction fetch
   • 19. 19. Decode
   • 20. 20. Register rename
   • 21. 21. Write to RS
   • 22. 22. Read from RS
   • 23. 23. Execute
   • 24. 24. Commit
   • 25. 25. Branch Prediction on the P6
   • 26. 26. The P6 Back End
   • 27. 27. CISC, RISC, and Instruction Set Translation [cool! explanation about ISA, CISC and RISC]
   • 28. 28. The P6 Microarchitecture’s Instruction Decoding Unit
   • 29. 29. The Cost of x86 Legacy Support on the P6
3. 30. Summary: The P6 Microarchitecture in Historical Context
4. 31. The Pentium Pro
5. 32. The Pentium II
6. 33. The Pentium III
7. 34. Conclusion

6. PowerPC Processors: 600 Series, 700 Series, And 7400

1. 1. A Brief History of PowerPC
2. 2. The PowerPC 601
   • The 601's Pipeline and Front End
   • The PowerPC Instruction Queue
   • Instruction Scheduling on the 601
   • The 601's Back End
     • The Integer Unit
     • The Floating-Point Unit
     • The Branch Execution Unit
     • The Sequencer Unit
   • Latency and Throughput Revised
   • Summary: The 601 in Historical Context
3. 3. The PowerPC 603 and 603e
   • The 603e's Back End
   • The 603e's Front End, Instruction Window, and Branch Prediction
   • Summary: The 603 and 603e in Historical Context
4. 4. The PowerPC 604
   • The 604's Pipeline and Back End
   • The 604's Front End and Instruction Window
   • The Issue Phase: The 604's Reservation Stations
   • The Four Rules of Instruction Dispatch
   • The in-order dispatch rule
   • The issue buffer/execution unit availability rule
   • The completion buffer availability rule
   • The rename register availability rule The Completion Phase: The 604's Reorder Buffer
   • Summary: The 604 in Historical Context
5. 5. The PowerPC 604e
6. 6. The PowerPC 750 (aka the G3)
   • The 750's Front End, Instruction Window, and Branch Instruction
   • Summary: The PowerPC 750 in Historical Context
7. 7. The PowerPC 7400 (aka the G4)
   • The G4's Vector Unit
   • Summary: The PowerPC G4 in Historical Context
8. 8. Conclusion

7. Intel's Pentium 4 vs Motorola's G4e - Approaches And Design Philosophies

1. 1. The Pentium 4’s Speed Addiction
2. 2. The General Approaches and Design Philosophies of the Pentium 4 and G4e
3. 3. An Overview of the G4e’s Architecture and Pipeline
4. 4. Stages 1 and 2: Instruction Fetch
5. 5. Stage 3: Decode/Dispatch
6. 6. Stage 4: Issue
7. 7. Stage 5: Execute
8. 8. Stages 6 and 7: Complete and Write-Back
9. 9. Branch Prediction on the G4e and Pentium 4
10. 10. An Overview of the Pentium 4’s Architecture
11. 11. Expanding the Instruction Window
12. 12. The Trace Cache
13. 13. Shortening Instruction Execution Time
14. 14. The Trace Cache’s Operation
15. 15. An Overview of the Pentium 4’s Pipeline
16. 16. Stages 1 and 2: Trace Cache Next Instruction Pointer
17. 17. Stages 3 and 4: Trace Cache Fetch
18. 18. Stage 5: Drive
19. 19. Stages 6 Through 8: Allocate and Rename (ROB)
20. 20. Stage 9: Queue
21. 21. Stages 10 Through 12: Schedule
22. 22. Stages 13 and 14: Issue
23. 23. Stages 15 and 16: Register Files
24. 24. Stage 17: Execute
25. 25. Stage 18: Flags
26. 26. Stage 19: Branch Check
27. 27. Stage 20: Drive
28. 28. Stages 21 and Onward: Complete and Commit
29. 29. The Pentium 4’s Instruction Window
30. 30. Summary.

8. 64-bit Computing and x86-64

1. 1. Intel’s IA-64 and AMD’s x86-64
2. 2. Why 64 Bits?
3. 3. What Is 64-Bit Computing?
4. 4. Current 64-Bit Applications
   • Dynamic Range
   • The Benefits of Increased Dynamic Range, or, How the Existing 64-Bit Computing Market Uses 64-Bit Integers
   • Virtual Address Space vs. Physical Address Space
   • The Benefits of a 64-Bit Address
5. 5. The 64-Bit Alternative: x86-64
   • Extended Registers
   • More Registers
   • Switching Modes
   • Out with the Old
6. 6. Conclusion

11. Understanding Caching And Performance

1. 1. Caching Basics
   • 2. 2. The Level 1 Cache
   • 3. 3. The Level 2 Cache
   • 4. 4. Example: A Byte’s Brief Journey Through the Memory Hierarchy
   • 5. 5. Cache Misses
2. 6. Locality of Reference
   • 7. 7. Spatial Locality of Data
   • 8. 8. Spatial Locality of Code
   • 9. 9. Temporal Locality of Code and Data
   • 10. 10. Locality: Conclusions
3. 11. Cache Organization: Blocks and Block Frames
4. 12. Tag RAM
5. 13. Fully Associative Mapping
6. 14. Direct Mapping
7. 15. N-Way Set Associative Mapping
   • 16. 16. Four-Way Set Associative Mapping
   • 17. 17. Two-Way Set Associative Mapping
   • 18. 18. Two-Way vs. Direct-Mapped
   • 19. 19. Two-Way vs. Four-Way
   • 20. 20. Associativity: Conclusions
8. 21. Temporal and Spatial Locality Revisited: Replacement/Eviction Policies and Block Sizes
9. 22. Types of Replacement/Eviction Policies
   • 23. 23. Block Sizes
10. 24. Write Policies: Write-Through vs. Write-Back
11. 25. Conclusions