SHLD regression

[Tiecoon]

The capstone next branch 05b3fbf is now disassembling improper opcode details for SHLD

With the following code

from capstone import *

CODE = b"\x0f\xa5\xc2\xd3"

md = Cs(CS_ARCH_X86, CS_MODE_64)
md.detail = True

for i in md.disasm(CODE, 0x1000):
    print("0x%x:\t%s\t%s\t\t%s" % (i.address, i.mnemonic, i.op_str, i.opcode))
    for j in i.opcode:
        print("\t" + hex(j))

4.0.1:

Name: capstone
Version: 4.0.1
Summary: Capstone disassembly engine
Home-page: http://www.capstone-engine.org
Author: Nguyen Anh Quynh
Author-email: aquynh@gmail.com
License: UNKNOWN
Location: /home/luke/.virtualenvs/...
Requires:
Required-by:

Produces:

0x1000: shld    edx, eax, cl            [15, 165, 0, 0]
        0xf
        0xa5
        0x0
        0x0

05b3fbf:

Name: capstone
Version: 5.0.0
Summary: Capstone disassembly engine
Home-page: http://www.capstone-engine.org
Author: Nguyen Anh Quynh
Author-email: aquynh@gmail.com
License: UNKNOWN
Location: /home/luke/.virtualenvs/...
Requires:
Required-by:

Produces

0x1000: shld    edx, eax, cl            [165, 0, 0, 0]
        0xa5
        0x0
        0x0
        0x0

[aquynh]

This is confused: what is wrong? Can you show the issue with our tool "cstool", so you dont need to write code? cstool also has -d option to show instruction details.

[aquynh]

So 1 byte is missing in opcode?

[Tiecoon]

yes the opcode is showing up as 0xa5 instead of 0xf 0x15

heres the output from cstool on the next branch

./cstool -d x32 \x0f\xa5\xc2\xd3                                                                                                                       next
 0  0f a5 c2                                         shld       edx, eax, cl
        ID: 684 (shld)
        Prefix:0x00 0x00 0x00 0x00
        Opcode:0xa5 0x00 0x00 0x00
        rex: 0x0
        addr_size: 4
        modrm: 0xc2
        disp: 0x0
        sib: 0x0
        op_count: 3
                operands[0].type: REG = edx
                operands[0].size: 4
                operands[0].access: READ | WRITE
                operands[1].type: REG = eax
                operands[1].size: 4
                operands[1].access: READ
                operands[2].type: REG = cl
                operands[2].size: 1
        Registers read: cl edx eax
        Registers modified: eflags edx
        EFLAGS: MOD_CF MOD_SF MOD_ZF MOD_PF UNDEF_OF UNDEF_AF

on master

 0  0f a5 c2                                         shld       edx, eax, cl
        Prefix:0x00 0x00 0x00 0x00
        Opcode:0x0f 0xa5 0x00 0x00
        rex: 0x0
        addr_size: 4
        modrm: 0xc2
        disp: 0x0
        sib: 0x0
        op_count: 3
                operands[0].type: REG = edx
                operands[0].size: 4
                operands[0].access: READ | WRITE
                operands[1].type: REG = eax
                operands[1].size: 4
                operands[1].access: READ
                operands[2].type: REG = cl
                operands[2].size: 1
        Registers read: cl edx eax
        Registers modified: eflags edx
        EFLAGS: MOD_CF MOD_SF MOD_ZF MOD_PF UNDEF_OF UNDEF_AF

[Tiecoon]

looking at my other issue its opcode also seems to get truncated. #1504

[aquynh]

dont use "master", but "next". (currently "master" is similar to "v4")

[aquynh]

ok will look into this issue soon

[aquynh]

fixed now in "next" branch, please confirm.

[Tiecoon]

Thanks! appears to be fixed.