Hello! It seems that in PPC the branch instructions incorrectly determine implicit register accesses, while some conditional instructions do not determine them at all. I expect branches and conditionals to be in agreement - conditionals write to conditional register or CTR (when applicable), while branches read corresponding register.
Here are some examples:
beq
Currently:
Reads: [CTR, RM]
Writes: [CTR]
Operands: [IMM]
Expected:
Reads: [CR0]
Writes: []
Operands: [IMM]
Not sure what is RM register and whether it is warranted here.
blt (explicit)
Currently:
Reads: [CTR, RM]
Writes: [CTR]
Operands: [CR7, IMM]
Expected:
Reads: []
Writes: []
Operands: [CR7, IMM]
Here CR7 is correctly determined as it is an explicit operand, but the incorrect implicits still present.
bdnz
Currently and expected:
Reads: [CTR]
Writes: [CTR]
Operands: [IMM]
Here implicit CTR read and write is correct, but there is a different problem of bdnz not being identified as conditional branch, and not given bc value.
cmpwi
Currently:
Reads: []
Writes: []
Operands: [REG, IMM]
Expected:
Reads: []
Writes: [CR0]
Operands: [REG, IMM]
rlwinm.
Currently and expected:
Reads: []
Writes: [CR0]
Operands: [REG, REG, IMM, IMM, IMM]
Here CR0 is correctly determined for instruction with dot suffix in addition to update_cr0 flag being set.
fcmpu (explicit)
Currently and expected:
Reads: []
Writes: []
Operands: [CR7, REG, REG]
Here CR7 is correctly determined as it is an explicit operand.
P.S. There is also another related issue of operands not supporting access flags, like in ARM for example, only implicit accesses are determined. But I suppose that feature is simply unsupported for PPC at the moment.
Hello! It seems that in PPC the branch instructions incorrectly determine implicit register accesses, while some conditional instructions do not determine them at all. I expect branches and conditionals to be in agreement - conditionals write to conditional register or CTR (when applicable), while branches read corresponding register.
Here are some examples:
beq
Currently:
Expected:
Not sure what is
RMregister and whether it is warranted here.blt (explicit)
Currently:
Expected:
Here
CR7is correctly determined as it is an explicit operand, but the incorrect implicits still present.bdnz
Currently and expected:
Here implicit
CTRread and write is correct, but there is a different problem ofbdnznot being identified as conditional branch, and not givenbcvalue.cmpwi
Currently:
Expected:
rlwinm.
Currently and expected:
Here
CR0is correctly determined for instruction with dot suffix in addition toupdate_cr0flag being set.fcmpu (explicit)
Currently and expected:
Here
CR7is correctly determined as it is an explicit operand.P.S. There is also another related issue of operands not supporting access flags, like in ARM for example, only implicit accesses are determined. But I suppose that feature is simply unsupported for PPC at the moment.