[x86] regression on `rcl` with capstone v5

[wargio]

d110 should ouput rcl dword [eax], 1 but instead returns rcl dword [eax]
This is the output on objdump

0:  d1 10                   rcl    DWORD PTR [eax],1 

[XVilka]

https://c9x.me/x86/html/file_module_x86_id_273.html

capstone/build on  next                                                                                                                                                                                    15:46:11
ℤ ./cstool -d x32 d110
 0  d1 10                                            rcl	dword ptr [eax]
	ID: 615 (rcl)
	Prefix:0x00 0x00 0x00 0x00
	Opcode:0xd1 0x00 0x00 0x00
	rex: 0x0
	addr_size: 4
	modrm: 0x10
	disp: 0x0
	sib: 0x0
	op_count: 1
		operands[0].type: MEM
			operands[0].mem.base: REG = eax
		operands[0].size: 4
		operands[0].access: READ
	Registers read: eax
	Registers modified: eflags
	EFLAGS: MOD_CF UNDEF_OF

[XVilka]

Bisecting pointed to this:

git bisect good
5a99624074d56f8eea26699496f0e8dc41cbf3fb is the first bad commit
commit 5a99624074d56f8eea26699496f0e8dc41cbf3fb
Author: Nguyen Anh Quynh <aquynh@gmail.com>
Date:   Tue Feb 26 15:19:51 2019 +0800

    sync with LLVM 7.0.1. X86 is first

[momo5502]

I'm in need for a fix for this issue. Usually I would try to contibute a fix myself, however I currently lack the time. So I want to at least bump this issue :D

[Rot127]

LLVM 18 disassembles without 1:

echo "0xd1,0x10" | llvm-mc-18 --disassemble --arch=x86 --show-encoding --output-asm-variant=1
	.text
	rcl	dword ptr [eax]                 # encoding: [0xd1,0x10]

Please check what is the correct syntax and open an issue with the LLVM-project.

[Rot127]

@wargio Can you please check against llvm-mc?

[wargio]

According to the ISA, that 1 should be there. https://c9x.me/x86/html/file_module_x86_id_273.html
so it is likely a regression of llvm or a decision taken to remove that field for one bit rotation.