SAIL based module generator

[Rot127]

Tracking issue for the SAIL generator

TODO: Add intro (please ping here if I forgot to add one and you need an explanation)

Current work

• WIP generator developed by @moste00: https://github.com/moste00/riscv_disasm_from_sail/
  • It is planned to generate an up-to-date RISC-V module.
• First module implementation initial implementation of the Sail-generated RISCV disassembler module #2498

Architectures to update with such a generator:

• RISC-V
• x86

[amkerrr]

Thanks for working on this. By the way, is there any schedule when up to date RISCV disassembler will be included in capstone? It seems B/V extensions support are missing right now.

[Rot127]

Short answer is: No schedule, but can be anything from 2-3 months (in an experimental branch, possibly but unlikely next) up to 1-2 years (in next branch + released).

As explanation:

The disassembler @moste00 is currently building is the first prototype. But what I've heard so far (couldn't find the time yet to check for myself), I am pretty sure it will be way better than the current module.

Personally, I would merge it into next the moment it produces the same result as the old one and is similarity/better tested. Which can be as early as in ~2-3 months. But @moste00 is a GSOC student of the Rizin and builds the disassembler for a different task (uplifting). So he doesn't have the responsibility to polish it to Capstone level. The moment it is working for him good enough he probably wants to go on with his other tasks.
But we will merge it into an experimental branch, which is based on the newest next.
So you can also use this one then, if you are not required to pin to a commit.

[Rot127]

Obsolete with #2756

The SAIL implementation was too complex and threw up too many problems.
If you'd like to know details please ask here.