RISCV support ISRV32/ISRV64

[fanfuqiang]

This is based on PR#1198 and LLVM upstream commit b81d715c(Sat Feb 16 18:39:14 2019).
Also referenced the SyestemZ TableGen patchs.
I also add the TableGen patch at capstone/contrib/update_riscv.

[fanfuqiang]

do you want to add the alias register FP to riscv.h?

Need add OPT? I will fix this when the RISCVC PR.
Maybe riscv will change assembler syntax.

[aquynh]

do you want to add the alias register FP to riscv.h?

Need add OPT? I will fix this when the RISCVC PR.
Maybe riscv will change assembler syntax.

i mean simply add this to riscv.h:

RISCV_REG_FP = RISCV_REG_S0

if you dont want to, never mind.

[fanfuqiang]

do you want to add the alias register FP to riscv.h?

Need add OPT? I will fix this when the RISCVC PR.
Maybe riscv will change assembler syntax.

i mean simply add this to riscv.h:

RISCV_REG_FP = RISCV_REG_S0

if you dont want to, never mind.

looks like already fixed, will depend on current instruction print s0/fp.
because I changed the RISCV_reg_name use the auto-generated register table.
And the removed reg_name_maps[] is used to contain the old s0/fp.

[aquynh]

there is one issue: you are using internal autogen register names, so the public register ID must follow the enum in RISCVGenRegisterInfo.inc.

you can see that cs_reg_name calls RISCV_reg_name(), which calls getRegisterName(). for this to work, the RISC_REG_xxx must match the enum in RISCVGenRegisterInfo.inc. however, these dont match, for example:

    RISCV_REG_F0_64,                                                                  
    RISCV_REG_F1_64,    

meanwhile:

  RISCV_F0_64 = 34,
  RISCV_F1_32 = 35,

you did not have this problem before, when you used reg_name_maps[]

now you can either make them match, or recover that reg_name_maps[]

[aquynh]

the mismatch starts from floating point registers, but not before that. this is why we dont have see any issues with test_riscv.c

another thing: given the current approach, we need to have alias registers in riscv.h. otherwise, we have:

0x1098:	srl	ra, sp, gp
	op_count: 3
		operands[0].type: REG = ra
		operands[1].type: REG = sp
		operands[2].type: REG = gp

users may ask where these RA, SP, GP registers are from, as they are nowhere in riscv.h.

(after update riscv.h, please update riscv_const.py by: cd bindings; make)

[aquynh]

one more issue is that RISCV_reg_name() should check the regid boundary, and return NULL if the ID is out of range. but right now getRegisterName() does this with assert(RegNo && RegNo < 97 && "Invalid register number!");, which aborts, and should be fixed.

[fanfuqiang]

there is one issue: you are using internal autogen register names, so the public register ID must follow the enum in RISCVGenRegisterInfo.inc.

you can see that cs_reg_name calls RISCV_reg_name(), which calls getRegisterName(). for this to work, the RISC_REG_xxx must match the enum in RISCVGenRegisterInfo.inc. however, these dont match, for example:

    RISCV_REG_F0_64,                                                                  
    RISCV_REG_F1_64,    

meanwhile:

  RISCV_F0_64 = 34,
  RISCV_F1_32 = 35,

you did not have this problem before, when you used reg_name_maps[]

now you can either make them match, or recover that reg_name_maps[]

fix consistency with RISCVGenRegisterInfo.inc.

[aquynh]

there is one issue: you are using internal autogen register names, so the public register ID must follow the enum in RISCVGenRegisterInfo.inc.
you can see that cs_reg_name calls RISCV_reg_name(), which calls getRegisterName(). for this to work, the RISC_REG_xxx must match the enum in RISCVGenRegisterInfo.inc. however, these dont match, for example:

    RISCV_REG_F0_64,                                                                  
    RISCV_REG_F1_64,    

meanwhile:

  RISCV_F0_64 = 34,
  RISCV_F1_32 = 35,

you did not have this problem before, when you used reg_name_maps[]
now you can either make them match, or recover that reg_name_maps[]

fix consistency with RISCVGenRegisterInfo.inc.

cool, lets finish this with alias registers added to riscv.h (then update binding constants after that)

[aquynh]

That is just S0, but how about all other alias registers?

[fanfuqiang]

That is just S0, but how about all other alias registers?

s0 and fp just the public printable register name, I can not understand what is the alias register?
there is only one, just ont s0 and fp for riscv::x8 about this. no more.

[aquynh]

For ex, look at the output of test_riscv.c, what is s1 register? There is no such a thing in riscv.h.

[fanfuqiang]

For ex, look at the output of test_riscv.c, what is s1 register? There is no such a thing in riscv.h.

I write after the comments.
OK, I add them all.

[aquynh]

No, we need the alias that users can use, not just comments. And please uppercase, like "FP", "S0", but not "fp", "s0".

[aquynh]

RISCV_REG_X8_s0

Please just use RISCV_REG_S0

[fanfuqiang]

No, we need the alias that users can use, not just comments. And please uppercase, like "FP", "S0", but not "fp", "s0".

what's the difference???

[aquynh]

Just to align with the current naming scheme.

[aquynh]

i will merge. please stay around to help to maintain this work.

[aquynh]

merged, thanks everyone for the amazing effort!

[fanfuqiang]

merged, thanks everyone for the amazing effort!

cheers, hope have the opportunity to see you offline.

[aquynh]

Hope to see you in BJ, i guess?

[fanfuqiang]

Hope to see you in BJ, i guess?
hope so