AArch64 update to LLVM 18

.github/workflows/CITest.yml

@@ -132,7 +132,6 @@ jobs:
           clang -lcapstone src/test_arm64_compatibility_header.c -o test_arm64_compatibility_header
         fi
         ./test_arm64_compatibility_header
-        cd "$(git rev-parse --show-toplevel)"
 
     - name: cstool - reaches disassembler engine
       run: |

.github/workflows/auto-sync.yml

@@ -66,3 +66,8 @@ jobs:
       - name: Test Header patcher
         run: |
           python -m unittest src/autosync/Tests/test_header_patcher.py
+          python -m unittest src/autosync/Tests/test_mcupdater.py
+
+      - name: Differ - Test save file is up-to-date
+        run: |
+          ./src/autosync/cpptranslator/Differ.py -a AArch64 --check_saved

.github/workflows/clang-tidy.yml

@@ -26,6 +26,10 @@ jobs:
         CC=clang sudo cmake --build . --config Release
         cd ..
 
+    - name: Install clang-tidy-15
+      run: |
+        sudo apt install clang-tidy-15
+
     - name: Check for warnings
       env:
         base_sha: ${{ github.event.pull_request.base.sha }}

CMakeLists.txt

@@ -890,6 +890,7 @@ if(CAPSTONE_BUILD_CSTEST)
         PREFIX extern
         GIT_REPOSITORY "https://git.cryptomilk.org/projects/cmocka.git"
         GIT_TAG "origin/stable-1.1"
+        GIT_SHALLOW true
         CONFIGURE_COMMAND cmake -DBUILD_SHARED_LIBS=OFF ../cmocka_ext/
         BUILD_COMMAND cmake --build . --config Release
         INSTALL_COMMAND ""

MCInst.c

@@ -1,6 +1,5 @@
 /* Capstone Disassembly Engine */
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
 #if defined(CAPSTONE_HAS_OSXKERNEL)
 #include <Availability.h>
 #include <libkern/libkern.h>
@@ -11,6 +10,7 @@
 #include <string.h>
 #include <assert.h>
 
+#include "MCInstrDesc.h"
 #include "MCInst.h"
 #include "utils.h"
 
@@ -105,12 +105,12 @@ bool MCOperand_isValid(const MCOperand *op)
 
 bool MCOperand_isReg(const MCOperand *op)
 {
-	return op->Kind == kRegister;
+	return op->Kind == kRegister || op->MachineOperandType == kRegister;
 }
 
 bool MCOperand_isImm(const MCOperand *op)
 {
-	return op->Kind == kImmediate;
+	return op->Kind == kImmediate || op->MachineOperandType == kImmediate;
 }
 
 bool MCOperand_isFPImm(const MCOperand *op)
@@ -224,16 +224,26 @@ bool MCInst_isPredicable(const MCInstrDesc *MIDesc)
 /// Checks if tied operands exist in the instruction and sets
 /// - The writeback flag in detail
 /// - Saves the indices of the tied destination operands.
-void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDesc)
-{
-	const MCOperandInfo *OpInfo = InstDesc[MCInst_getOpcode(MI)].OpInfo;
-	unsigned short NumOps = InstDesc[MCInst_getOpcode(MI)].NumOperands;
+void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDescTable, unsigned tbl_size)
+{
+	const MCInstrDesc *InstDesc = NULL;
+	const MCOperandInfo *OpInfo = NULL;
+	unsigned short NumOps = 0;
+	if (MI->csh->arch == CS_ARCH_ARM) {
+		// Uses old (pre LLVM 18) indexing method.
+		InstDesc = &InstDescTable[MCInst_getOpcode(MI)];
+		OpInfo = InstDescTable[MCInst_getOpcode(MI)].OpInfo;
+		NumOps = InstDescTable[MCInst_getOpcode(MI)].NumOperands;
+	} else {
+		InstDesc = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size);
+		OpInfo = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size)->OpInfo;
+		NumOps = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size)->NumOperands;
+	}
 
-	unsigned i;
-	for (i = 0; i < NumOps; ++i) {
+	for (unsigned i = 0; i < NumOps; ++i) {
 		if (MCOperandInfo_isTiedToOp(&OpInfo[i])) {
 			int idx = MCOperandInfo_getOperandConstraint(
-				&InstDesc[MCInst_getOpcode(MI)], i,
+				InstDesc, i,
 				MCOI_TIED_TO);
 
 			if (idx == -1)

MCInst.h

@@ -159,7 +159,7 @@ void MCInst_addOperand2(MCInst *inst, MCOperand *Op);
 
 bool MCInst_isPredicable(const MCInstrDesc *MIDesc);
 
-void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDesc);
+void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDescTable, unsigned tbl_size);
 
 bool MCInst_opIsTied(const MCInst *MI, unsigned OpNum);
 

MCInstrDesc.c

@@ -38,4 +38,11 @@ int MCOperandInfo_getOperandConstraint(const MCInstrDesc *InstrDesc,
 		return (OpInfo.Constraints >> ValuePos) & 0xf;
 	}
 	return -1;
-}
+}
+
+/// Returns the instruction description for the given MCInst opcode.
+/// Function should be called like:
+/// MCInstrDesc_get(MCInst_getOpcode(MI), ARCHInstDesc, ARR_SIZE(ARCHInstDesc));
+const MCInstrDesc *MCInstrDesc_get(unsigned opcode, const MCInstrDesc *table, unsigned tbl_size) {
+	return &table[tbl_size - 1 - opcode];
+}

MCInstrDesc.h

@@ -163,5 +163,9 @@ bool MCOperandInfo_isTiedToOp(const MCOperandInfo *m);
 int MCOperandInfo_getOperandConstraint(const MCInstrDesc *OpInfo,
 				       unsigned OpNum,
 				       MCOI_OperandConstraint Constraint);
+const MCInstrDesc *MCInstrDesc_get(unsigned opcode,
+                                   const MCInstrDesc *table,
+                                   unsigned tbl_size);
+
 
 #endif

MCRegisterInfo.h

@@ -23,7 +23,7 @@
 
 /// An unsigned integer type large enough to represent all physical registers,
 /// but not necessarily virtual registers.
-typedef uint16_t MCPhysReg;
+typedef int16_t MCPhysReg;
 typedef const MCPhysReg* iterator;
 
 typedef struct MCRegisterClass2 {

Mapping.h

@@ -31,6 +31,7 @@ typedef struct insn_map {
 	union {
 		ppc_suppl_info ppc;
 		loongarch_suppl_info loongarch;
+		aarch64_suppl_info aarch64;
 	} suppl_info; // Supplementary information for each instruction.
 #endif
 } insn_map;