tricore: fixes #2474

[b1llow]

Your checklist for this pull request

• I've documented or updated the documentation of every API function and struct this PR changes.
• I've added tests that prove my fix is effective or that my feature works (if possible)

Detailed description

• Removed the tricore td files as they will be updated in the llvm-capstone repository.
• Updated LLVM version to llvm18.
• Fixed tricore td files

ref capstone-engine/llvm-capstone#63

Test plan

...

Closing issues

closes #2474

[b1llow]

I added the A15 register to the Defs attribute, but this only has implicit register modification information, and there is still no A15 in the operands meta information.

let Defs = [A15] in
...

cstool -d tc162 d800
 0  d8 00  ld.a a15, [sp]#0
        ID: 164 (ld.a)
        op_count: 1
                operands[0].type: IMM = 0x0
                        .access: READ
        Registers modified: a15
        Groups: HasV120_UP

cc @Rot127

[Rot127]

Mh, I think we can go the expensive way for now. If one of the implicit registers commonly used in the asm text (a15, a10 etc.) are in the implicit list, check if they are in the asm text (with strstr()). if yes, insert them at the correct position.

So basically:

• a15 in implicit read/write?
• If yes: Check if a15 in asm text
• If yes: insert into details.

Same for the other registers like a10.

[Rot127]

Just had another idea. What if you add another operand class in the td files. For those registers.
You can assign a printing method to them. And a decoding method. For example: printImplicitA15(), printImplicitA10().
The decoding methods do nothing. And the print methods just adds the register to the details.
Do you think this would be easier?

[b1llow]

Both PRs should be ready for review now. @Rot127

cc @XVilka

[Rot127]

It looks like the correct fix. Very nice! So far it only fixes the ld.a instruction.

But we need also the other ones (see comment below. Effectively, all instructions with operands in TriCoreGenAsmWriter.inc::AsmStrs).

Just an observation: We never use TriCoreGenInstrInfo.inc::TriCoreInstrTable::ImplicitOps. Maybe they are a way to a quick fix? E.g. you can save them in an MCInst field and after printing, check if those names appear in the asm text.

But they seem to miss D15 and the access information. So only a little bit useful.
Maybe it misses D15 because they have the same value as A15?

No idea on what commit I clicked. PR LGTM. Please just add more tests for each instruction fixed now.

• Tests in test/issues/ or details
• Add TriCore to .github/workflows/auto-sync.yaml with the other architectures.

[Rot127]

Excellent! Thanks a lot.

Please just open an issue about the known access problems.

[XVilka]

@Rot127 please take a look again, it looks good to merge, I think.

[Rot127]

@kabeor

[kabeor]

Thanks again!