Init DecodeComplete with false to prevent build warnings.#34
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XVilka merged 1 commit intocapstone-engine:auto-syncfrom Sep 11, 2023
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Init DecodeComplete with false to prevent build warnings.#34XVilka merged 1 commit intocapstone-engine:auto-syncfrom
XVilka merged 1 commit intocapstone-engine:auto-syncfrom
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Files with unresolved conflicts: llvm/utils/TableGen/InstrInfoEmitter.cpp llvm/utils/TableGen/RegisterInfoEmitter.cpp llvm/utils/TableGen/SearchableTableEmitter.cpp llvm/utils/TableGen/SubtargetEmitter.cpp ================================================== LLVM 17 auto-sync update This commit squashed all commits of the auto-sync branch (which is based on LLVM 16). This squashed version is used to ease the rebase onto LLVM 17. For the complete commit history please see the auto-sync branch (https://github.com/capstone-engine/llvm-capstone/commits/auto-sync) To enable searching the commit messages are reproduces below as well: -------------------------------------------------- Emit a single header for all files. Captialize Target name for enums. Add lay metric to emit enum value for Banked and system regs. Malloc substr Sort instructions in ascending order. Free substr after use Add vanished constrainsts Fix `regInfoEmitEnums()` and indent Fix `GenDisassemblerTables.inc#checkDecoderPredicate()` Fix `TriCoreGenRegisterInfo.inc` | `PrinterCapstone::regInfoEmitRegClasses` revert changes to NEON instructions Add instructions with duplicate operands as Matchables. Add memory load and store info Correct memory access and out operand info Set register lists again as read ops due to llvm/llvm-project#62455 Make printAliasInstr and getMnemonic static. Generate CS instruction enums from actual mnemonic. Not via the flawed AsmMatcher. Fix typo in InstrInfoEmitter.cpp Add deprecated QPX feature Replace + and - with p and m Add AssemblerPredicates to PPC Generate RegEncodingTable Define functions which are called by the Mapper as static. Necessary because these functions are present in each arch' Remove set_mem_access(). The cases where this is used to mark access to actual memory operands are either very rare, or those are neon lane indicies. Generate correct op type for absolute addresses. Check for RegisterPointer operands first to prevent mis-categorization. Add missing Operand types Generate Instruction formats for PPC. Add Paired Single instructions. Partly revert 94e41ce (introduces accidentially removed code.) Set correct operand types for PS operands Add memory read/write attributes Add missing operand types Add mayLoad and mayStore information. Add documentation. Handle special AArch64 operand Replace C++ with C code. Check for duplicate enum instr. names Check for duplicate defintions of system registers. Add note about missing target names. Resolve templates in a single static method and add docs about it. Revert printing target name in upper case. Revert partially C++ syntax fixes in .td files. They break the TemplateCOllector since it searches for exactly those references but can't find any' Add all SubtargetFeatures to feature enum. Not just the one used by CGIs. Pass Decoder Enable to check specific table fields to determine if reg enum must be emitted. Allow to add namespace to type name/ Formatting Rework emitting of tables. The system operands are now emitted in reg, imm and aliass groups. Also a bug was fixed which emitted incorrect code.. Check for rename IMPLICIT_IMM operand types Pass DecodeComplete as pointer not as reference Print undef when it needs to be printed. Add namespace ids to all types and functions. Rework C translation. Pass MCOp as pointer not as ref Add missing SysImm type Fix syntax mistakes Generate additonal sys immediates and op groups. Handle edge case for printSVERegOp Handle default arguments of template functions. Add two missing op groups Generate a static RecEncodingTable Set enum values to encodings of the sys ops Generate a single Enum value file for system operands. Replace System operand groups with their operand types Fix missing braces warning Emit MCOperand validator. Emit lookupByName functions for sys operands Add namespaces for ARM. Check for Target if default arguments of template functions are resolved. auto-sync opcode & operand encoding info generation (#14) * Added operand and opcode info generation * Wrapped deprecated macro under an intellisense check Basically intellisense fails, causing multiple errors in other files, so when intellisense parses the code it will use the different version of the macro * Fixed a small bug Used double braces to prevent an old bug Removed extra new line and fixed a bug regarding move semantics Add mayStore to store instructions. Add writeback register and constraint to RFEI instructions. Do not prepend a tab character before alias mnemonics Remove invalid information, clearify certain points (remove passive, simplify word choice). Add writeback information to STC and LDC instructions. Specify the uninion member for each enum value. Fix: emit PC relative operand printers. Emit decoding function for PPC for 4byte wide instr. but with 64bit value. Add missing implicit defs of LR to branches. (#24) Emit a space if the alias has one at position I as well. Fix prefix instructions, set correct type. Add missing operand type to P10 memory operands. Emit Instruction Alias enums and mnemonic map. Formatting Change order of members so the match a name_map type Mark LI as CodeGenOnly, so it doesn't gets in conflict with the LI alias. Don't emit the NULL entry, because it prevents extending the table manually. Add branch alias and remove their instruction definition. Add alias for non always branch conditional branches. Fix: Cond braches with BH != 0 have no alias. Add support for PS S12 immediates. Tblgen capstone backends - add Alpha architecture (#17) Patch multiple occurrence of templates in a single string. Determine memory operands by there membership of patterns. Operands can be defined via patterns. The pattern has a type itself. Patterns are commonly used to define memory operands (as a collection of multiple other operands). Here we check, if the operand is part of a pattern with type iPTR. Type iPTR indicates a memory operand. Formatting Recurse into Pattern fragments. Allows to determine iPTR types also for operands part of Pattern fragments. Search for unspecified instruction patterns and extract memory op info from them. AArch64 has the case of patterns which are not set in the CGI class. Instead those patterns are free floating in the record keeper. With this commit we first collect all such unassigned patterns and save them in a map (indexed by instruction name they belong to). When instruction operand details are generated, the operand type is searched in the pattern of the instruction. If there is an operand with the same type in the pattern, which is also of a iPTR pattern, we treat it as memory operand. Note that we can not compare the operands of the instruction and the pattern operands by name. Because they simply are not named the same way -.- This is a short coming in the td files and should be addressed in LLVM. Because it is enormiously hard to get a 1 to 1 mapping from a pattern to an instruction and its operands. Fix case of empty op type. Fix: Pass operand name because it can not be determined by the Record. Always check operand names. Also if the type names are checked. Enable matching of op types via super classes. Give up and just search for memory operands in the asm string. Initialize DecodeComplete with true (as originally.) Operate on temporary MCInst when trying decode. Init DecodeComplete with false to prevent build warnings. (#34) normalize mnemonics before emitting them as string. Add printer for ADR operands. The ADR immediate operand is PC relative. But it misses its own printing function (in comparision to ADRP for example). If during disassembly the immediate was not resolved to a symbol (which is always the case for CS and llvm-objdump) the immediate is printed as is. Although it should print Address + Imm. This case should now be handled in printAdrLabel() Remove unused code If DoShift is false the fhist amount is 0 Add memory operand type to offset immediates. Only search for non memory operand in the syntax. Add memory operand type to authenticated load/store offsets Add missing init of DecodeComplete (#35) Set correct operand types for CIX instructions. Add CS_OP_MEM type to all operands of type iPTR. Set crbit type to Register (since it is treaded like this in the printer). Fix issue in LLVM-Auto-Updater.yml Debug LLVM-Auto-Updater.yml Update LLVM-Auto-Updater.yml Update LLVM-Auto-Updater.yml Update LLVM-Auto-Updater.yml Update LLVM-Auto-Updater.yml Update LLVM-Auto-Updater.yml Update LLVM-Auto-Updater.yml Update LLVM-Auto-Updater.yml Update LLVM-Auto-Updater.yml Fix issue in LLVM-Auto-Updater.yml
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