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Merged
lategoodbye merged 1 commit into from
Sep 25, 2025
Merged

arm64: dts: imx93-charge-som-testfixture: Rebuild DTS #17

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294 changes: 226 additions & 68 deletions arch/arm64/boot/dts/freescale/imx93-charge-som-testfixture.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -3,81 +3,162 @@
* Copyright (C) 2025 chargebyte GmbH
*/

#include "imx93-charge-som-dc-evb.dts"
/dts-v1/;

#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "imx93-charge-som.dtsi"

/ {
model = "chargebyte Charge SOM test fixture";
compatible = "chargebyte,imx93-charge-som-testfixture", "chargebyte,imx93-charge-som",
"phytec,imx93-phycore-som", "fsl,imx93";

aliases {
/delete-property/ rtc0;
/delete-property/ rtc1;
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1grp>;
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};
};

/delete-node/ &rv3028;
reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2grp>;
compatible = "regulator-fixed";
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-boot-on;
};

&flexcan1 {
status = "disabled";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VCC_SD";
};

&gpio3 {
/delete-node/ PCIe_NW_DISABLE; // remove GPIO hog
reg_vdd_3v3: regulator-vdd-3v3 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VDD_IO_3V3";
};

// Avoid conflict with Heartbeat LED on phyCore
/delete-node/ leds;
};

&gpio4 {
/delete-node/ PCIe_N_RESET; // remote GPIO hog
&ethphy1 {
ti,leds-polarity = <0>; // active-low
};

&iomuxc {
pinctrl_usdhc3_default: usdhc3grp {
fsl,pins = <
MX93_PAD_GPIO_IO22__USDHC3_CLK 0x179e
MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000139e
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000139e
>;
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
scl-gpios = <&gpio1 00 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 01 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";

eeprom@50 {
compatible = "microchip,24c256";
reg = <0x50>;
pagesize = <64>;
};
};

pinctrl_lpspi3: lpspi3grp {
/* drive strength: X2, slew rate: fast, no pull */
fsl,pins = <
MX93_PAD_GPIO_IO08__GPIO2_IO08 0x186 // SPI_EXT_CS0
MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x186
MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x186
MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x186
>;
&lpspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi3>;
num-cs = <1>;
cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
status = "okay";

flash@0 {
compatible = "winbond,w25q128", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
#address-cells = <1>;
#size-cells = <1>;

partition@0 {
label = "testdata";
reg = <0x0 0x100000>; // 1 MB
};
};
};

&lpuart4 {
status = "disabled";
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
over-current-active-low;
dr_mode = "host";
status = "okay";
};

&lpuart5 {
status = "disabled";
&usbotg2 {
vbus-supply = <&reg_usb_otg2_vbus>;
disable-over-current;
dr_mode = "host";
status = "okay";
};

&reg_can {
status = "disabled";
&gpio1 {
// 16 pins (0..15)
gpio-line-names = "I2C1_SCL", "I2C1_SDA", "", "", "", "", "LPUART2_RX", "LPUART2_TX", "CAN1_TX", "CAN1_RX", \
"CHSTOP_IN", "SPI_TPM_nCS0", "", "", "", "";
};

&tpm5 {
status = "disabled";
&gpio2 {
// 30 pins (0..29)
gpio-line-names = "SPI_PLC_nCS0", "", "", "", "", "", "", "SPI_PLC_nINT0", "X11_SPI_EXT_CS0", "X11_SPI_EXT_MISO", \
"X11_SPI_EXT_MOSI", "X11_SPI_EXT_CLK", "", "", "LPUART4_TX", "LPUART4_RX", "", "LPUART4_RTS_B", "BACKLIGHT_PWM", "", \
"", "", "X11_I2C5_SDA", "X11_I2C5_SCL", "USER_RED", "X11_CAN2_TX", "X11_PWM5_3", "X11_CAN2_RX", "", "";
};

&lpi2c1 {
eeprom@50 {
compatible = "microchip,24c256";
reg = <0x50>;
pagesize = <64>;
};
&gpio3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog3>, <&pinctrl_clko>;
// 32 pins (0..31)
gpio-line-names = "SD2_nCD", "", "", "", "", "", "", "SD2_nRESET", "", "", \
"", "", "", "", "", "", "", "", "", "", \
"", "X11_SD3_CMD", "X11_SD3_D0", "X11_SD3_D1", "X11_SD3_D2", "X11_SD3_D3", "X11_GPIO3_26", "X11_GPIO3_27", "LPUART5_RX", "LPUART5_RTS_B", \
"PCIe_NW_DISABLE", "LPUART5_TX";
};

&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_hog4>, <&pinctrl_ws2812b>;
// 30 pins (0..29)
gpio-line-names = "USB1_ID", "", "RTC_nINT", "USB2_OC", "USB1_OC", "", "PCIe_N_RESET", "DL_REQ_INTR_SPI", "USB2_PWREN", "nPLC_RESET_INT", \
"", "WS2812B", "SAFETY_BOOTMODE_SET", "USB1_PWREN_GPIO", "", "DISPLAY_EN", "", "", "", "", \
"", "SOM_EEPROM_WP", "", "SOM_RESET_PHY", "", "", "CAN1_EN", "PMIC_IRQ_B", "nSAFETY_RESET_INT", "SPI_TPM_nINT0";
};

/* SD card 1: limited to 50 MHz due to long cable by omitting pin mode 100/200 MHz */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_default>, <&pinctrl_usdhc2_cd>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
disable-wp;
no-sdio;
no-mmc;
status = "okay";
};

/* SD card 2: limited to 50 MHz due to long cable by omitting pin mode 100/200 MHz;
Expand All @@ -93,31 +174,108 @@
status = "okay";
};

&user_leds {
status = "disabled";
};
&iomuxc {

&user_keys {
status = "disabled";
};
/delete-node/ pinctrl_leds;

&lpspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi3>;
num-cs = <1>;
cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
status = "okay";
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
>;
};

flash@0 {
compatible = "winbond,w25q128", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
#address-cells = <1>;
#size-cells = <1>;
pinctrl_usdhc2_cd: usdhc2cdgrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
>;
};

partition@0 {
label = "testdata";
reg = <0x0 0x100000>; // 1 MB
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_default: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x179e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};

pinctrl_usdhc3_default: usdhc3grp {
fsl,pins = <
MX93_PAD_GPIO_IO22__USDHC3_CLK 0x179e
MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000139e
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000139e
>;
};

pinctrl_lpi2c1: lpi2c1grp {
/* sion, drive strength: X2, slew rate: fast, pull up, open drain */
fsl,pins = <
MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b86
MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b86
>;
};

pinctrl_lpi2c1_gpio: lpi2c1gpiogrp {
fsl,pins = <
MX93_PAD_I2C1_SCL__GPIO1_IO00 0x40000b9e
MX93_PAD_I2C1_SDA__GPIO1_IO01 0x40000b9e
>;
};

pinctrl_lpspi3: lpspi3grp {
/* drive strength: X2, slew rate: fast, no pull */
fsl,pins = <
MX93_PAD_GPIO_IO08__GPIO2_IO08 0x186 // SPI_EXT_CS0
MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x186
MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x186
MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x186
>;
};

pinctrl_usbotg1grp: usb1grp {
fsl,pins = <
MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x31e
MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e // USB1_PWREN_GPIO
// MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 not connected
>;
};

pinctrl_usbotg2grp: usb2grp {
fsl,pins = <
MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x31e // unused
MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e // USB2_PWREN
>;
};

pinctrl_hog3: hog3grp {
fsl,pins = <
MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x31e // PCIe_NW_DISABLE
>;
};

pinctrl_hog4: hog4grp {
fsl,pins = <
MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e // PCIe_N_RESET
>;
};

pinctrl_ws2812b: ws2812b {
fsl,pins = <
MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e // WS2812B
>;
};

pinctrl_clko: clkogrp {
fsl,pins = <
MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
>;
};
};