Welcome to the repository of warp, an open source processor core IP targeting the RISC-V instruction set architecture. Specifically, it is a dual issue in order architecture supporting the RV64GCBV architecture, plus privileged mode and various other minor extensions.
Warp is early in development. It currently executes most of the base RV32I and RV64I instruction set, with the exception of shift, load/store, and environment calls. An exhaustive instruction support list is below:
- add, sub, or, and, xor, slt, sltu
- addi, ori, andi, xori, slti, sltiu
- lui, auipc
- beq, bne, blt, bltu, bge, bgeu
- jal, jalr
- addw, subw
- addiw