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Merged
opsiff merged 7 commits into from
Sep 4, 2024
Merged

[RISCV] fix: Use WRITE_ONCE() when setting page table entries #398

opsiff merged 7 commits into from
Sep 4, 2024

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@RevySR
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@RevySR RevySR commented Sep 3, 2024

membarrier: riscv: Add full memory barrier in switch_mm()
riscv: Use WRITE_ONCE() when setting page table entries

andrea-parri and others added 7 commits September 3, 2024 21:06
@andrea-parri @RevySR
membarrier: riscv: Add full memory barrier in switch_mm()
be052d1 
The membarrier system call requires a full memory barrier after storing
to rq->curr, before going back to user-space.  The barrier is only
needed when switching between processes: the barrier is implied by
mmdrop() when switching from kernel to userspace, and it's not needed
when switching from userspace to kernel.

Rely on the feature/mechanism ARCH_HAS_MEMBARRIER_CALLBACKS and on the
primitive membarrier_arch_switch_mm(), already adopted by the PowerPC
architecture, to insert the required barrier.

Fixes: fab957c ("RISC-V: Atomic and Locking Code")
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-2-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
@palmer-dabbelt @RevySR
Merge patch series "membarrier: riscv: Core serializing command"
df1fec1 
RISC-V was lacking a membarrier implementation for the store/fetch
ordering, which is a bit tricky because of the deferred icache flushing
we use in RISC-V.

* b4-shazam-merge:
  membarrier: riscv: Provide core serializing command
  locking: Introduce prepare_sync_core_cmd()
  membarrier: Create Documentation/scheduler/membarrier.rst
  membarrier: riscv: Add full memory barrier in switch_mm()

Link: https://lore.kernel.org/r/20240131144936.29190-1-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
@RevySR
riscv: Use WRITE_ONCE() when setting page table entries
e4a8b43 
To avoid any compiler "weirdness" when accessing page table entries which
are concurrently modified by the HW, let's use WRITE_ONCE() macro
(commit 20a004e ("arm64: mm: Use READ_ONCE/WRITE_ONCE when accessing
page tables") gives a great explanation with more details).

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20231213203001.179237-2-alexghiti@rivosinc.com
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
mm: Introduce pudp/p4dp/pgdp_get() functions
4cac026 
Instead of directly dereferencing page tables entries, which can cause
issues (see commit 20a004e ("arm64: mm: Use READ_ONCE/WRITE_ONCE when
accessing page tables"), let's introduce new functions to get the
pud/p4d/pgd entries (the pte and pmd versions already exist).

Note that arm pgd_t is actually an array so pgdp_get() is defined as a
macro to avoid a build error.

Those new functions will be used in subsequent commits by the riscv
architecture.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20231213203001.179237-3-alexghiti@rivosinc.com
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
riscv: mm: Only compile pgtable.c if MMU
da437b5 
All functions defined in there depend on MMU, so no need to compile it
for !MMU configs.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20231213203001.179237-4-alexghiti@rivosinc.com
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
riscv: Use accessors to page table entries instead of direct dereference
de63ddb 
As very well explained in commit 20a004e ("arm64: mm: Use
READ_ONCE/WRITE_ONCE when accessing page tables"), an architecture whose
page table walker can modify the PTE in parallel must use
READ_ONCE()/WRITE_ONCE() macro to avoid any compiler transformation.

So apply that to riscv which is such architecture.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Acked-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20231213203001.179237-5-alexghiti@rivosinc.com
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
@RevySR
symbol: gpl: export pud_offset/p4d_offset symbol
723b1de 
export pud_offset/p4d_offset symbol

Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
@deepin-ci-robot
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deepin-ci-robot commented Sep 3, 2024

deepin pr auto review

RISC-V: Fix memory barrier on rq->curr modification in scheduler.

Found by:

  • Marek target: riscv64-unknown-elf-gcc -c -o /dev/null /home/marcin/riscv-kernel/linux-5.12-um/arch/riscv/include/linux/sched.h
  • Marek target: riscv64-unknown-elf-gcc -c -o /dev/null /home/marcin/riscv-kernel/linux-5.12-um/arch/riscv/include/linux/sync_core.h

Signed-off-by: Marek Kobus 7f5b850f44d874279132030410830424d850f4@gmail.com

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deepin-ci-robot commented Sep 3, 2024

[APPROVALNOTIFIER] This PR is NOT APPROVED

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@RevySR RevySR changed the title riscv: Use WRITE_ONCE() when setting page table entries [RISCV] fix: Use WRITE_ONCE() when setting page table entries Sep 3, 2024
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opsiff commented Sep 4, 2024

/lgtm

@opsiff opsiff merged commit 6d2bace into deepin-community:linux-6.6.y Sep 4, 2024
@RevySR RevySR deleted the deepin/linux-6.6.y/riscv-mm branch September 4, 2024 04:51
opsiff pushed a commit that referenced this pull request Sep 4, 2024
@andrea-parri @opsiff
membarrier: riscv: Add full memory barrier in switch_mm()
52a0460 
mainline inclusion
from mainline-v6.9-rc1
link:#398

The membarrier system call requires a full memory barrier after storing
to rq->curr, before going back to user-space.  The barrier is only
needed when switching between processes: the barrier is implied by
mmdrop() when switching from kernel to userspace, and it's not needed
when switching from userspace to kernel.

Rely on the feature/mechanism ARCH_HAS_MEMBARRIER_CALLBACKS and on the
primitive membarrier_arch_switch_mm(), already adopted by the PowerPC
architecture, to insert the required barrier.

Fixes: fab957c ("RISC-V: Atomic and Locking Code")
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-2-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit d6cfd17)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
opsiff pushed a commit that referenced this pull request Sep 4, 2024
@andrea-parri @opsiff
membarrier: Create Documentation/scheduler/membarrier.rst
51166f6 
mainline inclusion
from mainline-v6.9-rc1
link:#398

To gather the architecture requirements of the "private/global
expedited" membarrier commands.  The file will be expanded to
integrate further information about the membarrier syscall (as
needed/desired in the future).  While at it, amend some related
inline comments in the membarrier codebase.

Suggested-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-3-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit a14d11a)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
opsiff pushed a commit that referenced this pull request Sep 4, 2024
@andrea-parri @opsiff
locking: Introduce prepare_sync_core_cmd()
3b0a39e 
mainline inclusion
from mainline-v6.9-rc1
link:#398

Introduce an architecture function that architectures can use to set
up ("prepare") SYNC_CORE commands.

The function will be used by RISC-V to update its "deferred icache-
flush" data structures (icache_stale_mask).

Architectures defining prepare_sync_core_cmd() static inline need to
select ARCH_HAS_PREPARE_SYNC_CORE_CMD.

Suggested-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-4-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit 4ff4c74)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
opsiff pushed a commit that referenced this pull request Sep 4, 2024
@andrea-parri @opsiff
membarrier: riscv: Provide core serializing command
9b78932 
mainline inclusion
from mainline-v6.9-rc1
link:#398

RISC-V uses xRET instructions on return from interrupt and to go back
to user-space; the xRET instruction is not core serializing.

Use FENCE.I for providing core serialization as follows:

 - by calling sync_core_before_usermode() on return from interrupt (cf.
   ipi_sync_core()),

 - via switch_mm() and sync_core_before_usermode() (respectively, for
   uthread->uthread and kthread->uthread transitions) before returning
   to user-space.

On RISC-V, the serialization in switch_mm() is activated by resetting
the icache_stale_mask of the mm at prepare_sync_core_cmd().

Suggested-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-5-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit cd9b290)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
opsiff pushed a commit that referenced this pull request Sep 4, 2024
@opsiff
riscv: Use WRITE_ONCE() when setting page table entries
7cd282b 
mainline inclusion
from mainline-v6.8-rc1
link:#398

To avoid any compiler "weirdness" when accessing page table entries which
are concurrently modified by the HW, let's use WRITE_ONCE() macro
(commit 20a004e ("arm64: mm: Use READ_ONCE/WRITE_ONCE when accessing
page tables") gives a great explanation with more details).

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20231213203001.179237-2-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit c30fa83)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
opsiff pushed a commit that referenced this pull request Sep 4, 2024
@opsiff
mm: Introduce pudp/p4dp/pgdp_get() functions
117b687 
mainline inclusion
from mainline-v6.8-rc1
link:#398

Instead of directly dereferencing page tables entries, which can cause
issues (see commit 20a004e ("arm64: mm: Use READ_ONCE/WRITE_ONCE when
accessing page tables"), let's introduce new functions to get the
pud/p4d/pgd entries (the pte and pmd versions already exist).

Note that arm pgd_t is actually an array so pgdp_get() is defined as a
macro to avoid a build error.

Those new functions will be used in subsequent commits by the riscv
architecture.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20231213203001.179237-3-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
(cherry picked from commit eba2591)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
opsiff pushed a commit that referenced this pull request Sep 4, 2024
@opsiff
riscv: mm: Only compile pgtable.c if MMU
a03b800 
mainline inclusion
from mainline-v6.8-rc1
link:#398

All functions defined in there depend on MMU, so no need to compile it
for !MMU configs.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20231213203001.179237-4-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
(cherry picked from commit d650899)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
opsiff pushed a commit that referenced this pull request Sep 4, 2024
@opsiff
riscv: Use accessors to page table entries instead of direct dereference
416066b 
mainline inclusion
from mainline-v6.8-rc1
link:#398

As very well explained in commit 20a004e ("arm64: mm: Use
READ_ONCE/WRITE_ONCE when accessing page tables"), an architecture whose
page table walker can modify the PTE in parallel must use
READ_ONCE()/WRITE_ONCE() macro to avoid any compiler transformation.

So apply that to riscv which is such architecture.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Acked-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20231213203001.179237-5-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
(cherry picked from commit edf9556)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
@MingcongBai MingcongBai mentioned this pull request Nov 12, 2024
Open
Avenger-285714 pushed a commit to Avenger-285714/wyl-linux-dev that referenced this pull request Apr 26, 2025
@andrea-parri
membarrier: Create Documentation/scheduler/membarrier.rst
6e3d5d0 
mainline inclusion
from mainline-v6.9-rc1
link:deepin-community/kernel#398

To gather the architecture requirements of the "private/global
expedited" membarrier commands.  The file will be expanded to
integrate further information about the membarrier syscall (as
needed/desired in the future).  While at it, amend some related
inline comments in the membarrier codebase.

Suggested-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-3-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit a14d11a)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
Avenger-285714 pushed a commit to Avenger-285714/wyl-linux-dev that referenced this pull request Apr 26, 2025
@andrea-parri
locking: Introduce prepare_sync_core_cmd()
63755bc 
mainline inclusion
from mainline-v6.9-rc1
link:deepin-community/kernel#398

Introduce an architecture function that architectures can use to set
up ("prepare") SYNC_CORE commands.

The function will be used by RISC-V to update its "deferred icache-
flush" data structures (icache_stale_mask).

Architectures defining prepare_sync_core_cmd() static inline need to
select ARCH_HAS_PREPARE_SYNC_CORE_CMD.

Suggested-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-4-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit 4ff4c74)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
Avenger-285714 pushed a commit to Avenger-285714/wyl-linux-dev that referenced this pull request Apr 26, 2025
@andrea-parri
membarrier: riscv: Provide core serializing command
15d6d0b 
mainline inclusion
from mainline-v6.9-rc1
link:deepin-community/kernel#398

RISC-V uses xRET instructions on return from interrupt and to go back
to user-space; the xRET instruction is not core serializing.

Use FENCE.I for providing core serialization as follows:

 - by calling sync_core_before_usermode() on return from interrupt (cf.
   ipi_sync_core()),

 - via switch_mm() and sync_core_before_usermode() (respectively, for
   uthread->uthread and kthread->uthread transitions) before returning
   to user-space.

On RISC-V, the serialization in switch_mm() is activated by resetting
the icache_stale_mask of the mm at prepare_sync_core_cmd().

Suggested-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-5-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit cd9b290)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
opsiff pushed a commit to opsiff/UOS-kernel that referenced this pull request Apr 27, 2025
@andrea-parri @opsiff
membarrier: Create Documentation/scheduler/membarrier.rst
1354e2f 
mainline inclusion
from mainline-v6.9-rc1
link:deepin-community#398

To gather the architecture requirements of the "private/global
expedited" membarrier commands.  The file will be expanded to
integrate further information about the membarrier syscall (as
needed/desired in the future).  While at it, amend some related
inline comments in the membarrier codebase.

Suggested-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-3-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit a14d11a)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
opsiff pushed a commit to opsiff/UOS-kernel that referenced this pull request Apr 27, 2025
@andrea-parri @opsiff
locking: Introduce prepare_sync_core_cmd()
7bce1c7 
mainline inclusion
from mainline-v6.9-rc1
link:deepin-community#398

Introduce an architecture function that architectures can use to set
up ("prepare") SYNC_CORE commands.

The function will be used by RISC-V to update its "deferred icache-
flush" data structures (icache_stale_mask).

Architectures defining prepare_sync_core_cmd() static inline need to
select ARCH_HAS_PREPARE_SYNC_CORE_CMD.

Suggested-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-4-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit 4ff4c74)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
opsiff pushed a commit to opsiff/UOS-kernel that referenced this pull request Apr 27, 2025
@andrea-parri @opsiff
membarrier: riscv: Provide core serializing command
28adbcf 
mainline inclusion
from mainline-v6.9-rc1
link:deepin-community#398

RISC-V uses xRET instructions on return from interrupt and to go back
to user-space; the xRET instruction is not core serializing.

Use FENCE.I for providing core serialization as follows:

 - by calling sync_core_before_usermode() on return from interrupt (cf.
   ipi_sync_core()),

 - via switch_mm() and sync_core_before_usermode() (respectively, for
   uthread->uthread and kthread->uthread transitions) before returning
   to user-space.

On RISC-V, the serialization in switch_mm() is activated by resetting
the icache_stale_mask of the mm at prepare_sync_core_cmd().

Suggested-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-5-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit cd9b290)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
opsiff pushed a commit to opsiff/UOS-kernel that referenced this pull request May 9, 2025
@andrea-parri @opsiff
membarrier: Create Documentation/scheduler/membarrier.rst
0be32b8 
mainline inclusion
from mainline-v6.9-rc1
link:deepin-community#398

To gather the architecture requirements of the "private/global
expedited" membarrier commands.  The file will be expanded to
integrate further information about the membarrier syscall (as
needed/desired in the future).  While at it, amend some related
inline comments in the membarrier codebase.

Suggested-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-3-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit a14d11a)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
opsiff pushed a commit to opsiff/UOS-kernel that referenced this pull request May 9, 2025
@andrea-parri @opsiff
locking: Introduce prepare_sync_core_cmd()
a42a400 
mainline inclusion
from mainline-v6.9-rc1
link:deepin-community#398

Introduce an architecture function that architectures can use to set
up ("prepare") SYNC_CORE commands.

The function will be used by RISC-V to update its "deferred icache-
flush" data structures (icache_stale_mask).

Architectures defining prepare_sync_core_cmd() static inline need to
select ARCH_HAS_PREPARE_SYNC_CORE_CMD.

Suggested-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-4-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit 4ff4c74)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
opsiff pushed a commit to opsiff/UOS-kernel that referenced this pull request May 9, 2025
@andrea-parri @opsiff
membarrier: riscv: Provide core serializing command
9e3e0f6 
mainline inclusion
from mainline-v6.9-rc1
link:deepin-community#398

RISC-V uses xRET instructions on return from interrupt and to go back
to user-space; the xRET instruction is not core serializing.

Use FENCE.I for providing core serialization as follows:

 - by calling sync_core_before_usermode() on return from interrupt (cf.
   ipi_sync_core()),

 - via switch_mm() and sync_core_before_usermode() (respectively, for
   uthread->uthread and kthread->uthread transitions) before returning
   to user-space.

On RISC-V, the serialization in switch_mm() is activated by resetting
the icache_stale_mask of the mm at prepare_sync_core_cmd().

Suggested-by: Palmer Dabbelt <palmer@dabbelt.com>
Signed-off-by: Andrea Parri <parri.andrea@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Link: https://lore.kernel.org/r/20240131144936.29190-5-parri.andrea@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
(cherry picked from commit cd9b290)
Signed-off-by: Wentao Guan <guanwentao@uniontech.com>
Avenger-285714 pushed a commit to Avenger-285714/DeepinKernel that referenced this pull request Dec 15, 2025
@fenghusthu
init: only move down lockup_detector_init() when sdei_watchdog is ena…
6401d93 
…bled

commit 1509d06c9c41985ee6b7dd6acbb08d9ee5dcf2b3 openEuler

When I enable CONFIG_DEBUG_PREEMPT and CONFIG_PREEMPT on X86, I got the
following Call Trace:

[    3.341853] BUG: using smp_processor_id() in preemptible [00000000] code: swapper/0/1
[    3.344392] caller is debug_smp_processor_id+0x17/0x20
[    3.344395] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.10.0+ deepin-community#398
[    3.344397] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.10.2-0-g5f4c7b1-prebuilt.qemu-project.org 04/01/2014
[    3.344399] Call Trace:
[    3.344410]  dump_stack+0x60/0x76
[    3.344412]  check_preemption_disabled+0xba/0xc0
[    3.344415]  debug_smp_processor_id+0x17/0x20
[    3.344422]  hardlockup_detector_event_create+0xf/0x60
[    3.344427]  hardlockup_detector_perf_init+0xf/0x41
[    3.344430]  watchdog_nmi_probe+0xe/0x10
[    3.344432]  lockup_detector_init+0x22/0x5b
[    3.344437]  kernel_init_freeable+0x20c/0x245
[    3.344439]  ? rest_init+0xd0/0xd0
[    3.344441]  kernel_init+0xe/0x110
[    3.344446]  ret_from_fork+0x22/0x30

It is because sched_init_smp() set 'current->nr_cpus_allowed' to
possible cpu number, and check_preemption_disabled() failed. This issue
is introduced by commit bf4c2c61cc74 ("lockup_detector: init lockup detector after all the init_calls"), which moves down
lockup_detector_init() after do_basic_setup(). Fix it by moving
lockup_detector_init() to its origin place when sdei_watchdog is
disabled. There is no problem when sdei_watchdog is enabled because
watchdog_nmi_probe() is overridden in
'arch/arm64/kernel/watchdog_sdei.c' in this case.

Fixes: 8747ebe027bd ("lockup_detector: init lockup detector after all the init_calls")
Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Reviewed-by: Wei Li <liwei391@huawei.com>
Signed-off-by: Chen Jun <chenjun102@huawei.com>
Signed-off-by: huwentao <huwentao19@h-partners.com>
Signed-off-by: yeyiyang <850219375@qq.com>
Signed-off-by: WangYuli <wangyl5933@chinaunicom.cn>
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@RevySR @deepin-ci-robot @opsiff @andrea-parri @palmer-dabbelt