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[Deepin-Kernel-SIG] [linux 6.6-y] [Hygon] Hygon: Update drivers' support for Hygon model 4h, 6h~8h and 10h processors #601
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[Deepin-Kernel-SIG] [linux 6.6-y] [Hygon] Hygon: Update drivers' support for Hygon model 4h, 6h~8h and 10h processors #601
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Add HID HYGO0030 to support Hygon GPIO controller. Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
Add kernel parameter set_guest_pat_wb to set guest PAT to WB in some non-passthrough application scenarios to enhance performance. Signed-off-by: Yanjing Zhou <zhouyanjing@hygon.cn> Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
…h model 4h When booting in guest on Hygon family 18h model 4h platform, there is warning as follows: "Hygon Fam18h Model4h northbridge init failed(-19)!" Avoid the northbridge init failure warning in guest since there is no northbridge. Fixes: dc29574 ("x86/amd_nb: Add northbridge support for Hygon family 18h model 4h") Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
Get the correct cs id in die interleave scenario for Hygon family 18h model 4h. Fixes: f7aa404 ("EDAC/amd64: Adjust address translation for Hygon family 18h model 4h") Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
The width of die/socket id mask and cs fabric id is extended to 11 bits since Hygon family 18h model 4h, so use u16 for those variables which are also suitable for all other older generation Hygon processors. Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
…odel 6h On Hygon family 18h model 6h platform, each DDR has two subchannels, and each subchannel has a mca bank with a cs corresponded. In the process of address translation, it needs to know the instance id of cs to access df register correctly. The instance id of cs can be calculated from IPID[23:20] and IPID[13]: IPID[23:20] represents which umc controller it belongs to, and IPID[13] represents which subchannel it is. Fixes: 47ed942 ("EDAC/amd64: Adjust UMC channel for Hygon family 18h model 6h") Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
The intlv_num_dies should be get from F0x60[1:0] for Hygon family 18h model 6h. Fixes: a6712ab ("EDAC/amd64: Add support for Hygon family 18h model 6h") Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
The error types are changed in LS and IF machine check control registers of Hygon family 18h model 7h processors, so add support to get the correct error types in smca error decoding process. Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
The DF ID is get from DF F5 device for Hygon family 18h model 7h processors. Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
The SB IOAPIC for Hygon family 18h model 10h processors is also on the device 0xb. Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
Add hygon_f18h_m10h() to identify Hygon family 18h model 10h processors. Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
Add umc address translation support for Hygon family 18h model 10h. Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
…l 10h For Hygon family 18h model 10h processor, channels without memory are gated. As a result, all bits in relevant registers are set to 1, which cause the edac driver initializing incorrectly. So add support to check if the umc channel is effectively enabled. Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
Get the correct DDR memory types for Hygon family 18h model 10h. Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
The instance id for Hygon family 18h model 10h is also get from IPID[23:20] and IPID[13]. Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
Add Hygon family 18h model 8h processor support for amd_nb. Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
Add Hygon family 18h model 8h processor support for amd64_edac. Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
…ssor The commit 69fe5f1 ("perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and later") changed amd_f17h_perfmon_event_map to amd_zen1_perfmon_event_map which is limited to processors only with X86_FEATURE_ZEN1. This makes some event counters such as cache-misses and cache-references can not be tracked on Hygon family 18h processors. When using perf tool to monitor performance, the result will be listed as follows: 0 cache-miesses # 0.000 % of all cache refs 0 cache-references So add perfmon_event_map support for Hygon family 18h processors to fix the incorrect display. Fixes: 69fe5f1 ("perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and later") Signed-off-by: Liao Xuan <liaoxuan@hygon.cn>
Reviewer's Guide by SourceryThis pull request updates several drivers (EDAC, MCE, KVM, IOMMU, GPIO) to add or improve support for Hygon family 18h model 4h, 6h~8h and 10h processors. The EDAC driver is updated to properly map memory addresses and handle UMC channel enabling. The MCE driver is updated to include Hygon-specific error strings. The KVM driver is updated to allow setting the guest PAT to WB for performance enhancement. The IOMMU driver is updated to recognize the new processor models. The GPIO driver is updated to recognize Hygon GPIO devices. Sequence diagram for UMC error decodingsequenceDiagram
participant CPU
participant EDAC Driver
participant UMC
CPU->>EDAC Driver: Reports MCE (Machine Check Exception)
EDAC Driver->>EDAC Driver: decode_umc_error(node_id, mce)
EDAC Driver->>UMC: pvt->ops->get_err_info(m, &err)
alt hygon_f18h_m4h() && boot_cpu_data.x86_model >= 0x6 || hygon_f18h_m10h()
EDAC Driver->>EDAC Driver: umc = (err.channel << 1) + ((m->ipid & BIT(13)) >> 13)
else
EDAC Driver->>EDAC Driver: umc = err.channel
end
EDAC Driver->>UMC: Reads UMC registers to decode error
UMC-->>EDAC Driver: Error information
EDAC Driver->>CPU: Logs error information
Updated class diagram for amd64_pvt structclassDiagram
class amd64_pvt {
-const char *ctl_name
-int model
-flags
+void get_err_info(struct mce *m, struct amd64_error_info *err)
}
note for amd64_pvt "This class represents the AMD64 private data, which is updated to include the model number and a pointer to the error info function."
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Hey @Avenger-285714 - I've reviewed your changes and they look great!
Here's what I looked at during the review
- 🟢 General issues: all looks good
- 🟢 Security: all looks good
- 🟢 Testing: all looks good
- 🟡 Complexity: 1 issue found
- 🟢 Documentation: all looks good
Help me be more useful! Please click 👍 or 👎 on each comment and I'll use the feedback to improve your reviews.
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| /* Read DramOffset, check if base 1 is used. */ | ||
| if (hygon_f18h_m4h() && | ||
| if ((hygon_f18h_m4h() || hygon_f18h_m10h()) && |
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issue (complexity): Consider creating a helper function to abstract repeated Hygon variant checks.
Consider abstracting the repeated Hygon variant checks into helper functions to simplify the control flow. For example, you can create an inline helper to cover both conditions:
static inline bool is_hygon_variant(void) {
return hygon_f18h_m4h() || hygon_f18h_m10h();
}Then replace:
if ((hygon_f18h_m4h() || hygon_f18h_m10h()) &&
df_indirect_read_instance(nid, 0, 0x214, umc, &ctx.tmp))
goto out_err;with:
if (is_hygon_variant() &&
df_indirect_read_instance(nid, 0, 0x214, umc, &ctx.tmp))
goto out_err;Similarly, where you check both positive and negative conditions related to Hygon functions, reuse the helper:
if (!is_hygon_variant())
intlv_num_sockets = (ctx.tmp >> 8) & 0x1;This isolates the configuration‐specific logic from the main flow and minimizes duplicated branches while preserving functionality.
opsiff
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/lgtm
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[APPROVALNOTIFIER] This PR is APPROVED This pull-request has been approved by: opsiff, sourcery-ai[bot] The full list of commands accepted by this bot can be found here. The pull request process is described here DetailsNeeds approval from an approver in each of these files:
Approvers can indicate their approval by writing |
liaoxuan:
Update EDAC, NB, IOMMU, GPIO and KVM drivers for Hygon family 18h model 4h, 6h~8h and 10h processors.
Reference:
https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel/pulls/54
https://gitee.com/anolis/cloud-kernel/pulls/3366
Link: https://gitcode.com/deepin-community/kernel/pull/1
Summary by Sourcery
Update drivers for Hygon family 18h model 4h, 6h-8h, and 10h processors. This includes updates to EDAC, northbridge, IOMMU, GPIO, KVM, and performance monitoring drivers. Additionally, update MCE error descriptions for Hygon Model 7h processors and add support for setting guest PAT to WB to improve performance in non-passthrough scenarios.
Enhancements: