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Fix INDEX_ADDR codegen on ARM for large element sizes.#13639
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We were attempting to generate `base + index * size` using `MADD`, but had the registers in the wrong order and were generating `base * index + size`. This change fixes the register order s.t. the expected instruction is generated. Fixes #13593.
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sdmaclea
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Aug 29, 2017
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LGTM. I verified this fixed the regression on tip. Thanks
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@dotnet-bot |
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Windows ARM failures are due to missing tests; perf smoke tests are failing for reasons detailed elsewhere by @DrewScoggins. |
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@dotnet-bot test Tizen armel Cross Release Build |
jashook
approved these changes
Aug 30, 2017
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Superseded by #13701. |
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We were attempting to generate
base + index * sizeusingMADD, buthad the registers in the wrong order and were generating
base * index + size. This change fixes the register order s.t. theexpected instruction is generated.
Fixes #13593.