Add environment variable (COMPlus_EnableDiagnostics) to disable debuggging and profiling

[mikem8361]

This reverts commit e998512.

[mikem8361]

@RussKeldorph, @hseok-oh. @janvorli, @dotnet/arm32-contrib , @jkotas

I need help with armel Tizen leg that keeps fail with my changes. I don't have any idea how my changes are causing these tests to repeatable fail with my change, but master without my changes passes most of the time.

I don't have any hardware, access to any or the ramp time to repro this bug.

[alpencolt]

@sergign60 could you take a look?

[RussKeldorph]

@mikem8361 Have you tried your changes on a Raspberry Pi running Linux? That scenario is much closer to Linux/x64 and should be easier to investigate. If it doesn't repro there and only repros on Tizen, then I think we're going to have to enlist Samsung's help regardless.

[okodron]

@RussKeldorph, is current CI issue related with #12972?

[RussKeldorph]

@okodron We have chalked most of the intermittent Tizen qemu CI failures up to #6298. However, I've never seen as many tests fail in a single job as are failing on this PR. I think there's a good chance @mikem8361 is right that this PR is causing or exposing another issue. We would appreciate help in investigating.

@hqueue @hseok-oh

[mikem8361]

FYI @lt72

[lt72]

@hqueue @hseok-oh @okodron @sergign60: this issue is blocking one important scenario. Could any of you please see what the issue is that causes the problem?
We do not have the HW to try and repro and we would prefer not to have to do that anyway...

15:52:10 FAILED   - JIT/Directed/coverage/importer/ldelemnullarr2/ldelemnullarr2.sh
15:52:10                BEGIN EXECUTION
15:52:10                /home/coreclr/bin/tests/Windows_NT.x64.Checked/Tests/coreoverlay/corerun ldelemnullarr2.exe
15:52:10                qemu: Unsupported syscall: 389
15:52:10 
               ./ldelemnullarr2.sh: line 243:   370 Segmentation fault      (core dumped) $_DebuggerFullPath "$CORE_ROOT/corerun" $ExePath $CLRTestExecutionArguments```

[okodron]

All the test from tests/testsRunningInsideARM.txt pass on the real ARM Tizen device.

sh-3.2# ./runtest.sh --sequential --testRootDir=/home/owner/managed-tests/ --coreOverlayDir=/home/owner/coreclr/ --testNativeBinDir=/home/owner/tests/ --testDirFile=/home/owner/tests/testsRunningInsideARM.txt 
Running on  CPU- arm
Skipping crossgen of FX assemblies.
Skip preparing for GC stress test. Dependent package is not supported on this architecture.
The tests have been prepared
The tests have been prepared
         - JIT/Directed/coverage/importer/ldelemnullarr2/ldelemnullarr2.sh
The tests have been prepared
         - JIT/Methodical/Coverage/b39946/b39946.sh
The tests have been prepared
         - JIT/Methodical/tailcall/_il_dbgtest_3b/_il_dbgtest_3b.sh
The tests have been prepared
         - JIT/Regression/CLR-x86-JIT/V1-M09.5-PDC/b26863/b26863/b26863.sh
The tests have been prepared
         - JIT/Regression/CLR-x86-JIT/V1-M09.5-PDC/b28037/b28037/b28037.sh
The tests have been prepared
         - JIT/Regression/CLR-x86-JIT/V1-M09.5-PDC/b29068/b29068/b29068.sh
The tests have been prepared
         - JIT/Regression/CLR-x86-JIT/V1-M09.5-PDC/b32560/b32560/b32560.sh
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         - JIT/Regression/CLR-x86-JIT/V1-M11-Beta1/b31878/b31878/b31878.sh
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         - JIT/Regression/CLR-x86-JIT/V1-M11-Beta1/b37608/b37608/b37608.sh
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         - JIT/Regression/CLR-x86-JIT/V1-M11-Beta1/b39217/b39217/b39217.sh
The tests have been prepared
         - JIT/Regression/CLR-x86-JIT/V1-M11-Beta1/b39946/b39946/b39946.sh
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         - JIT/Regression/CLR-x86-JIT/V1-M11-Beta1/b41488/b41488/b41488.sh
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         - JIT/Regression/CLR-x86-JIT/V1-M12-Beta2/b47975/b47975/b47975.sh
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         - JIT/Regression/CLR-x86-JIT/V1-M12-Beta2/b49809/b49809/b49809.sh
The tests have been prepared
         - JIT/Regression/CLR-x86-JIT/V1-M12-Beta2/b80045/b80045/b80045.sh
The tests have been prepared
         - JIT/Regression/CLR-x86-JIT/V2.0-Beta2/b091942/b091942/b091942.sh
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         - JIT/Regression/VS-ia64-JIT/V1.2-M01/b12263/b12263/b12263.sh
The tests have been prepared
         - JIT/Regression/VS-ia64-JIT/V1.2-M02/b26496/b26496/b26496.sh
The tests have been prepared
         - JIT/Regression/VS-ia64-JIT/V2.0-RTM/b539509/b539509/b539509.sh
The tests have been prepared
         - JIT/SIMD/VectorReturn_ro/VectorReturn_ro.sh
         - Loader/classloader/methodoverriding/regressions/549411/exploit/exploit.sh

=======================
     Test Results
=======================
# CoreCLR Bin Dir  : 
# Tests Discovered : 23
# Passed           : 23
# Failed           : 0
# Skipped          : 0
=======================
2 minutes and 26 seconds taken to run CoreCLR tests.

It looks like the problem is in the qemu itself. However I'll check the presence of that "qemu-unsupported" membarrier() syscall.

[mikem8361]

@okodron please let me know when I can merge this PR. Thanks.

[okodron]

I used strace on Tizen ARM device and didn't find any calls of membarrier().
However liblttng-ust library uses membarrier() syscall via liburcu library. liblttng-ust was not loaded on my Tizen ARM device. Maybe it's loaded in qemu-environment and this leads to call of "unsupported" syscall due to the usage of old qemu 2.0.
I think this issue is only specific to old qemu ARM environment. There were another PRs (#16429 #16535) with the same Tizen CI issue.
@mikem8361 can you merge this PR with tests passing on a real device but failing on qemu?

[mikem8361]

What branch do you want me to merge? Master?

[mikem8361]

I just merged with the latest master.

[mikem8361]

I have another completely independent change in PR #16978 that is also failing the Tizen legs. I'm going merge this PR real soon now.

[okodron]

@mikem8361 , thank you!
I'll have a look at #16978 too.