Implement AVX/AVX2/SSE3 Load* intrinsics by fiigii · Pull Request #16200 · dotnet/coreclr

fiigii · 2018-02-04T19:36:58Z

fiigii · 2018-02-04T19:37:42Z

test Windows_NT x64 Checked jitincompletehwintrinsic
test Windows_NT x64 Checked jitx86hwintrinsicnoavx
test Windows_NT x64 Checked jitx86hwintrinsicnoavx2
test Windows_NT x64 Checked jitx86hwintrinsicnosimd
test Windows_NT x64 Checked jitnox86hwintrinsic

test Windows_NT x86 Checked jitincompletehwintrinsic
test Windows_NT x86 Checked jitx86hwintrinsicnoavx
test Windows_NT x86 Checked jitx86hwintrinsicnoavx2
test Windows_NT x86 Checked jitx86hwintrinsicnosimd
test Windows_NT x86 Checked jitnox86hwintrinsic

test Ubuntu x64 Checked jitincompletehwintrinsic
test Ubuntu x64 Checked jitx86hwintrinsicnoavx
test Ubuntu x64 Checked jitx86hwintrinsicnoavx2
test Ubuntu x64 Checked jitx86hwintrinsicnosimd
test Ubuntu x64 Checked jitnox86hwintrinsic

test OSX10.12 x64 Checked jitincompletehwintrinsic
test OSX10.12 x64 Checked jitx86hwintrinsicnoavx
test OSX10.12 x64 Checked jitx86hwintrinsicnoavx2
test OSX10.12 x64 Checked jitx86hwintrinsicnosimd
test OSX10.12 x64 Checked jitnox86hwintrinsic

tannergooding · 2018-02-05T03:29:16Z

 HARDWARE_INTRINSIC(SSE41_IsSupported,                                "get_IsSupported",                                  SSE41,      -1,           0,            0,           {INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid},           HW_Category_IsSupportedProperty,               HW_Flag_NoFlag)
 HARDWARE_INTRINSIC(SSE41_Multiply,                                   "Multiply",                                         SSE41,      -1,           16,           2,           {INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_pmuldq,    INS_invalid,   INS_invalid,   INS_invalid},           HW_Category_SimpleSIMD,                        HW_Flag_Commutative)
 HARDWARE_INTRINSIC(SSE41_BlendVariable,                              "BlendVariable",                                    SSE41,      -1,           16,           3,           {INS_pblendvb,  INS_pblendvb,  INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_invalid,   INS_blendvps,  INS_blendvpd},          HW_Category_SimpleSIMD,                        HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SSE41_LoadAlignedVector128NonTemporal,            "LoadAlignedVector128NonTemporal",                           SSE41,      -1,           16,           1,           {INS_movntdqa,  INS_movntdqa,  INS_movntdqa,  INS_movntdqa,  INS_movntdqa,  INS_movntdqa,  INS_movntdqa,  INS_movntdqa,  INS_invalid,   INS_invalid},           HW_Category_MemoryLoad,                        HW_Flag_NoFlag)                 


nit: alignment of fields is off

Thanks, will fix.

tannergooding · 2018-02-05T03:31:52Z

It would be useful to uncomment the ProcessInputs lines for Avx and Avx2 and to rerun the script: https://github.com/dotnet/coreclr/blob/master/tests/src/JIT/HardwareIntrinsics/X86/Shared/GenerateTests.csx#L169

The only thing blocking them (to my knowledge) was the LoadVector256 and LoadAlignedVector256 implementations.

tannergooding · 2018-02-05T03:32:05Z

Are you going to handle the Store intrinsics in a separate PR?

fiigii · 2018-02-05T03:35:59Z

Are you going to handle the Store intrinsics in a separate PR?

Yes, I will submit the store PR tomorrow.

4creators · 2018-02-05T18:38:30Z

Yes, I will submit the store PR tomorrow.
@fiigii will it comprise Sse2 as well?

fiigii · 2018-02-05T18:44:11Z

will it comprise Sse2 as well?

Yes, I will implement all Sse2.Store*.

fiigii · 2018-02-05T20:28:50Z

@CarolEidt @tannergooding RyuJIT emitter seems not support SSE4.1 movntdqa without VEX-encoding. I removed Sse41.LoadAlignedVector128NonTemporal from this PR and logged the issue at https://github.com/dotnet/coreclr/issues/16216.

Can we merge these Load intrinsics at first and implement Sse41.LoadAlignedVector128NonTemporal later? That would be good to test containment on Load*.

tannergooding · 2018-02-05T20:39:57Z

I agree that dropping the Sse41 4-byte instruction here and implementing it later is fine.

the SSE4.1 4-byte instructions in particular are blocked until https://github.com/dotnet/coreclr/issues/15908 is resolved.

fiigii · 2018-02-05T20:47:59Z

test Windows_NT x64 Checked jitincompletehwintrinsic
test Windows_NT x64 Checked jitx86hwintrinsicnoavx
test Windows_NT x64 Checked jitx86hwintrinsicnoavx2
test Windows_NT x64 Checked jitx86hwintrinsicnosimd
test Windows_NT x64 Checked jitnox86hwintrinsic

test Windows_NT x86 Checked jitincompletehwintrinsic
test Windows_NT x86 Checked jitx86hwintrinsicnoavx
test Windows_NT x86 Checked jitx86hwintrinsicnoavx2
test Windows_NT x86 Checked jitx86hwintrinsicnosimd
test Windows_NT x86 Checked jitnox86hwintrinsic

test Ubuntu x64 Checked jitincompletehwintrinsic
test Ubuntu x64 Checked jitx86hwintrinsicnoavx
test Ubuntu x64 Checked jitx86hwintrinsicnoavx2
test Ubuntu x64 Checked jitx86hwintrinsicnosimd
test Ubuntu x64 Checked jitnox86hwintrinsic

test OSX10.12 x64 Checked jitincompletehwintrinsic
test OSX10.12 x64 Checked jitx86hwintrinsicnoavx
test OSX10.12 x64 Checked jitx86hwintrinsicnoavx2
test OSX10.12 x64 Checked jitx86hwintrinsicnosimd
test OSX10.12 x64 Checked jitnox86hwintrinsic

fiigii · 2018-02-06T01:22:20Z

@tannergooding Do you know why do these OSX tests fail? There is no error message.

tannergooding · 2018-02-06T01:24:29Z

Looks like the machines had network issues. I have requeued the jobs.

fiigii · 2018-02-06T01:31:36Z

Thank you. Looks like unrelated failures.
Rebased to solve the conflict from SSE2 load.

fiigii · 2018-02-06T20:03:06Z

@CarolEidt Does this PR look good to you?

CarolEidt · 2018-02-06T21:13:54Z

It would be useful to uncomment the ProcessInputs lines for Avx and Avx2 and to rerun the script

It would be good to know if you have done that. If not, could you open an issue to enable the template for those?

CarolEidt

LGTM, but the conflicts need to be resolved before merging.

fiigii · 2018-02-06T21:52:23Z

@tannergooding @CarolEidt Thank for the review, I logged the containment test work at https://github.com/dotnet/coreclr/issues/16244. Will submit a PR soon.

fiigii · 2018-02-06T21:55:54Z

@CarolEidt May I have the permission to add PR/issues to "Hardware Intrinsic Project" if possible? That may save your time 😄

CarolEidt · 2018-02-06T21:58:22Z

May I have the permission to add PR/issues to "Hardware Intrinsic Project" if possible?

I'm not sure if that's possible - I don't see any permission settings, so I suspect that it uses the repo permisions.

Implement AVX/AVX2/SSE3 Load* intrinsics Commit migrated from dotnet/coreclr@5e94fd1

tannergooding reviewed Feb 5, 2018

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4creators mentioned this pull request Feb 5, 2018

Moving a number of the Sse2 hwintrinsic tests to use the test template. #16192

Merged

fiigii force-pushed the loadstore branch from 578fe66 to 45d7e0b Compare February 5, 2018 20:15

fiigii changed the title ~~Implement AVX/AVX2/SSE4.1/SSE3 Load* intrinsics~~ Implement AVX/AVX2/SSE3 Load* intrinsics Feb 6, 2018

fiigii force-pushed the loadstore branch from 45d7e0b to 074c2fe Compare February 6, 2018 01:29

tannergooding approved these changes Feb 6, 2018

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CarolEidt approved these changes Feb 6, 2018

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CarolEidt assigned fiigii Feb 6, 2018

FeiPengIntel added 3 commits February 6, 2018 13:44

Implement AVX LoadAlignedVector256, LoadDquVector256, and LoadVector256

c28ba7e

Implement SSE3 LoadAndDuplicateToVector128 and LoadDquVector128

8f2ff46

Implement AVX2 LoadAlignedVector256/128NonTemporal

747b121

fiigii force-pushed the loadstore branch from 074c2fe to 747b121 Compare February 6, 2018 21:45

CarolEidt merged commit 5e94fd1 into dotnet:master Feb 6, 2018

fiigii deleted the loadstore branch February 6, 2018 23:04

fiigii mentioned this pull request Jan 31, 2020

Enable containment test for AVX.LoadVector256/LoadAlignedVector256 dotnet/runtime#9678

Closed

picenka21 pushed a commit to picenka21/runtime that referenced this pull request Feb 18, 2022

Merge pull request dotnet/coreclr#16200 from fiigii/loadstore

0d98444

Implement AVX/AVX2/SSE3 Load* intrinsics Commit migrated from dotnet/coreclr@5e94fd1

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