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Sort out ARM load/store instruction size issues #20126

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CarolEidt merged 8 commits into from
May 30, 2019
Merged

Sort out ARM load/store instruction size issues #20126

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57fed86
Avoid using ins_Load/ins_Store with constant type
mikedn Oct 20, 2018
f8300eb
Use ldr to load array lengths/lower bounds
mikedn Oct 20, 2018
4863934
Use ldr to load array length (part 2)
mikedn Oct 20, 2018
ea3eae4
Stop the using the instruction size for immediate scaling on ARM32
mikedn Oct 20, 2018
f3ecb40
Stop using ldrsw for TYP_INT loads
mikedn Oct 20, 2018
a2fc3e9
Cleanup genCodeForIndir/genCodeForStoreInd
mikedn Oct 20, 2018
fda2253
Remove ARM32/64 load/store instruction size inconsistencies
mikedn Oct 20, 2018
cdd2b56
Remove unnecessary insUnscaleImm parameter
mikedn May 29, 2019
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15 changes: 6 additions & 9 deletions src/jit/codegenarm.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1287,12 +1287,11 @@ void CodeGen::genCodeForReturnTrap(GenTreeOp* tree)
//
void CodeGen::genCodeForStoreInd(GenTreeStoreInd* tree)
{
GenTree* data = tree->Data();
GenTree* addr = tree->Addr();
var_types targetType = tree->TypeGet();
emitter* emit = getEmitter();
GenTree* data = tree->Data();
GenTree* addr = tree->Addr();
var_types type = tree->TypeGet();

assert(!varTypeIsFloating(targetType) || (targetType == data->TypeGet()));
assert(!varTypeIsFloating(type) || (type == data->TypeGet()));

GCInfo::WriteBarrierForm writeBarrierForm = gcInfo.gcIsWriteBarrierCandidate(tree, data);
if (writeBarrierForm != GCInfo::WBF_NoBarrier)
Expand Down Expand Up @@ -1323,8 +1322,6 @@ void CodeGen::genCodeForStoreInd(GenTreeStoreInd* tree)
}
else // A normal store, not a WriteBarrier store
{
bool dataIsUnary = false;

// We must consume the operands in the proper execution order,
// so that liveness is updated appropriately.
genConsumeAddress(addr);
Expand All @@ -1334,13 +1331,13 @@ void CodeGen::genCodeForStoreInd(GenTreeStoreInd* tree)
genConsumeRegs(data);
}

if (tree->gtFlags & GTF_IND_VOLATILE)
if ((tree->gtFlags & GTF_IND_VOLATILE) != 0)
{
// issue a full memory barrier a before volatile StInd
instGen_MemoryBarrier();
}

emit->emitInsLoadStoreOp(ins_Store(targetType), emitTypeSize(tree), data->gtRegNum, tree);
getEmitter()->emitInsLoadStoreOp(ins_Store(type), emitActualTypeSize(type), data->gtRegNum, tree);
}
}

Expand Down
93 changes: 35 additions & 58 deletions src/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1180,13 +1180,13 @@ void CodeGen::genFuncletProlog(BasicBlock* block)

// Load the CallerSP of the main function (stored in the PSP of the dynamically containing funclet or
// function)
genInstrWithConstant(ins_Load(TYP_I_IMPL), EA_PTRSIZE, REG_R1, REG_R1,
genFuncletInfo.fiCallerSP_to_PSP_slot_delta, REG_R2, false);
genInstrWithConstant(INS_ldr, EA_PTRSIZE, REG_R1, REG_R1, genFuncletInfo.fiCallerSP_to_PSP_slot_delta,
REG_R2, false);
regSet.verifyRegUsed(REG_R1);

// Store the PSP value (aka CallerSP)
genInstrWithConstant(ins_Store(TYP_I_IMPL), EA_PTRSIZE, REG_R1, REG_SPBASE,
genFuncletInfo.fiSP_to_PSP_slot_delta, REG_R2, false);
genInstrWithConstant(INS_str, EA_PTRSIZE, REG_R1, REG_SPBASE, genFuncletInfo.fiSP_to_PSP_slot_delta, REG_R2,
false);

// re-establish the frame pointer
genInstrWithConstant(INS_add, EA_PTRSIZE, REG_FPBASE, REG_R1,
Expand All @@ -1201,8 +1201,8 @@ void CodeGen::genFuncletProlog(BasicBlock* block)
-genFuncletInfo.fiFunction_CallerSP_to_FP_delta, REG_R2, false);
regSet.verifyRegUsed(REG_R3);

genInstrWithConstant(ins_Store(TYP_I_IMPL), EA_PTRSIZE, REG_R3, REG_SPBASE,
genFuncletInfo.fiSP_to_PSP_slot_delta, REG_R2, false);
genInstrWithConstant(INS_str, EA_PTRSIZE, REG_R3, REG_SPBASE, genFuncletInfo.fiSP_to_PSP_slot_delta, REG_R2,
false);
}
}
}
Expand Down Expand Up @@ -1509,7 +1509,7 @@ BasicBlock* CodeGen::genCallFinally(BasicBlock* block)

if (compiler->lvaPSPSym != BAD_VAR_NUM)
{
getEmitter()->emitIns_R_S(ins_Load(TYP_I_IMPL), EA_PTRSIZE, REG_R0, compiler->lvaPSPSym, 0);
getEmitter()->emitIns_R_S(INS_ldr, EA_PTRSIZE, REG_R0, compiler->lvaPSPSym, 0);
}
else
{
Expand Down Expand Up @@ -1845,9 +1845,7 @@ void CodeGen::genCodeForLclVar(GenTreeLclVar* tree)
assert(targetType != TYP_STRUCT);

instruction ins = ins_Load(targetType);
emitAttr attr = emitTypeSize(targetType);

attr = varTypeIsFloating(targetType) ? attr : emit->emitInsAdjustLoadStoreAttr(ins, attr);
emitAttr attr = emitActualTypeSize(targetType);

emit->emitIns_R_S(ins, attr, tree->gtRegNum, varNum, 0);
genProduceReg(tree);
Expand Down Expand Up @@ -1907,9 +1905,7 @@ void CodeGen::genCodeForStoreLclFld(GenTreeLclFld* tree)

instruction ins = ins_Store(targetType);

emitAttr attr = emitTypeSize(targetType);

attr = varTypeIsFloating(targetType) ? attr : emit->emitInsAdjustLoadStoreAttr(ins, attr);
emitAttr attr = emitActualTypeSize(targetType);

emit->emitIns_S_R(ins, attr, dataReg, varNum, offset);

Expand Down Expand Up @@ -1986,9 +1982,7 @@ void CodeGen::genCodeForStoreLclVar(GenTreeLclVar* tree)
inst_set_SV_var(tree);

instruction ins = ins_Store(targetType);
emitAttr attr = emitTypeSize(targetType);

attr = varTypeIsFloating(targetType) ? attr : emit->emitInsAdjustLoadStoreAttr(ins, attr);
emitAttr attr = emitActualTypeSize(targetType);

emit->emitIns_S_R(ins, attr, dataReg, varNum, /* offset */ 0);

Expand Down Expand Up @@ -3208,13 +3202,6 @@ void CodeGen::genCodeForReturnTrap(GenTreeOp* tree)
//
void CodeGen::genCodeForStoreInd(GenTreeStoreInd* tree)
{
GenTree* data = tree->Data();
GenTree* addr = tree->Addr();
var_types targetType = tree->TypeGet();
emitter* emit = getEmitter();
emitAttr attr = emitTypeSize(tree);
instruction ins = ins_Store(targetType);

#ifdef FEATURE_SIMD
// Storing Vector3 of size 12 bytes through indirection
if (tree->TypeGet() == TYP_SIMD12)
Expand All @@ -3224,6 +3211,9 @@ void CodeGen::genCodeForStoreInd(GenTreeStoreInd* tree)
}
#endif // FEATURE_SIMD

GenTree* data = tree->Data();
GenTree* addr = tree->Addr();

GCInfo::WriteBarrierForm writeBarrierForm = gcInfo.gcIsWriteBarrierCandidate(tree, data);
if (writeBarrierForm != GCInfo::WBF_NoBarrier)
{
Expand All @@ -3247,8 +3237,6 @@ void CodeGen::genCodeForStoreInd(GenTreeStoreInd* tree)
}
else // A normal store, not a WriteBarrier store
{
bool dataIsUnary = false;
GenTree* nonRMWsrc = nullptr;
// We must consume the operands in the proper execution order,
// so that liveness is updated appropriately.
genConsumeAddress(addr);
Expand All @@ -3258,7 +3246,7 @@ void CodeGen::genCodeForStoreInd(GenTreeStoreInd* tree)
genConsumeRegs(data);
}

regNumber dataReg = REG_NA;
regNumber dataReg;
if (data->isContainedIntOrIImmed())
{
assert(data->IsIntegralConst(0));
Expand All @@ -3270,33 +3258,25 @@ void CodeGen::genCodeForStoreInd(GenTreeStoreInd* tree)
dataReg = data->gtRegNum;
}

assert((attr != EA_1BYTE) || !(tree->gtFlags & GTF_IND_UNALIGNED));
var_types type = tree->TypeGet();
instruction ins = ins_Store(type);

if (tree->gtFlags & GTF_IND_VOLATILE)
if ((tree->gtFlags & GTF_IND_VOLATILE) != 0)
{
bool useStoreRelease =
genIsValidIntReg(dataReg) && !addr->isContained() && !(tree->gtFlags & GTF_IND_UNALIGNED);
bool addrIsInReg = addr->isUsedFromReg();
bool addrIsAligned = ((tree->gtFlags & GTF_IND_UNALIGNED) == 0);

if (useStoreRelease)
if ((ins == INS_strb) && addrIsInReg)
{
switch (EA_SIZE(attr))
{
case EA_1BYTE:
assert(ins == INS_strb);
ins = INS_stlrb;
break;
case EA_2BYTE:
assert(ins == INS_strh);
ins = INS_stlrh;
break;
case EA_4BYTE:
case EA_8BYTE:
assert(ins == INS_str);
ins = INS_stlr;
break;
default:
assert(false); // We should not get here
}
ins = INS_stlrb;
}
else if ((ins == INS_strh) && addrIsInReg && addrIsAligned)
{
ins = INS_stlrh;
}
else if ((ins == INS_str) && genIsValidIntReg(dataReg) && addrIsInReg && addrIsAligned)
{
ins = INS_stlr;
}
else
{
Expand All @@ -3305,7 +3285,7 @@ void CodeGen::genCodeForStoreInd(GenTreeStoreInd* tree)
}
}

emit->emitInsLoadStoreOp(ins, attr, dataReg, tree);
getEmitter()->emitInsLoadStoreOp(ins, emitActualTypeSize(type), dataReg, tree);
}
}

Expand Down Expand Up @@ -4731,17 +4711,14 @@ void CodeGen::genSIMDIntrinsicGetItem(GenTreeSIMD* simdNode)
{
int offset = (int)index * genTypeSize(baseType);
instruction ins = ins_Load(baseType);
baseTypeSize = varTypeIsFloating(baseType)
? baseTypeSize
: getEmitter()->emitInsAdjustLoadStoreAttr(ins, baseTypeSize);

assert(!op1->isUsedFromReg());

if (op1->OperIsLocal())
{
unsigned varNum = op1->gtLclVarCommon.gtLclNum;

getEmitter()->emitIns_R_S(ins, baseTypeSize, targetReg, varNum, offset);
getEmitter()->emitIns_R_S(ins, emitActualTypeSize(baseType), targetReg, varNum, offset);
}
else
{
Expand All @@ -4752,7 +4729,7 @@ void CodeGen::genSIMDIntrinsicGetItem(GenTreeSIMD* simdNode)
regNumber baseReg = addr->gtRegNum;

// ldr targetReg, [baseReg, #offset]
getEmitter()->emitIns_R_R_I(ins, baseTypeSize, targetReg, baseReg, offset);
getEmitter()->emitIns_R_R_I(ins, emitActualTypeSize(baseType), targetReg, baseReg, offset);
}
}
else
Expand Down Expand Up @@ -5047,7 +5024,7 @@ void CodeGen::genStoreIndTypeSIMD12(GenTree* treeNode)
assert(tmpReg != addr->gtRegNum);

// 8-byte write
getEmitter()->emitIns_R_R(ins_Store(TYP_DOUBLE), EA_8BYTE, data->gtRegNum, addr->gtRegNum);
getEmitter()->emitIns_R_R(INS_str, EA_8BYTE, data->gtRegNum, addr->gtRegNum);

// Extract upper 4-bytes from data
getEmitter()->emitIns_R_R_I(INS_mov, EA_4BYTE, tmpReg, data->gtRegNum, 2);
Expand Down Expand Up @@ -5083,7 +5060,7 @@ void CodeGen::genLoadIndTypeSIMD12(GenTree* treeNode)
regNumber tmpReg = treeNode->GetSingleTempReg();

// 8-byte read
getEmitter()->emitIns_R_R(ins_Load(TYP_DOUBLE), EA_8BYTE, targetReg, addr->gtRegNum);
getEmitter()->emitIns_R_R(INS_ldr, EA_8BYTE, targetReg, addr->gtRegNum);

// 4-byte read
getEmitter()->emitIns_R_R_I(INS_ldr, EA_4BYTE, tmpReg, addr->gtRegNum, 8);
Expand Down Expand Up @@ -5126,7 +5103,7 @@ void CodeGen::genStoreLclTypeSIMD12(GenTree* treeNode)
regNumber tmpReg = treeNode->GetSingleTempReg();

// store lower 8 bytes
getEmitter()->emitIns_S_R(ins_Store(TYP_DOUBLE), EA_8BYTE, operandReg, varNum, offs);
getEmitter()->emitIns_S_R(INS_str, EA_8BYTE, operandReg, varNum, offs);

// Extract upper 4-bytes from data
getEmitter()->emitIns_R_R_I(INS_mov, EA_4BYTE, tmpReg, operandReg, 2);
Expand Down
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