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[Wasm RyuJit] asserts crossgenning wasm debug SPC #125756

@AndyAyersMS

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@AndyAyersMS

Debug SPC Asserts

Assertion failed 'isInitBlk == src->gtSkipReloadOrCopy()->IsInitVal()'

Single method repro args:--singlemethodtypename "System.Array" --singlemethodname "Ctor" --singlemethodindex 2
C:\repos\runtime2\src\coreclr\jit\gentree.h:9528
Assertion failed 'isInitBlk == src->gtSkipReloadOrCopy()->IsInitVal()' in 'System.Array:Ctor(ptr,uint,ptr):System.Array' during 'Linear scan register alloc' (IL size 25; hash 0xfb8a8728; MinOpts)

In the above the IR node is

N006 (???,???) [000007] --CXG+-----                    t7 = *  CALL r2r_ind int    System.Runtime.CompilerServices.ObjectHandleOnStack:Create[System.__Canon](byref):System.Runtime.CompilerServices.ObjectHandleOnStack
                                                            /--*  t7     int
N007 (???,???) [000016] DACXG+-----                         *  STORE_LCL_VAR struct<System.Runtime.CompilerServices.ObjectHandleOnStack, 4> V10 tmp3

and we seem to have an assumption that if the source of a block store is TYP_INT then the source must be an INIT_VAL.

Assertion failed 'emitTypeSizes[TypeGet(type)] > 0'

Single method repro args:--singlemethodtypename "System.GC" --singlemethodname "GetGCMemoryInfo" --singlemethodindex 2
C:\repos\runtime2\src\coreclr\jit\emit.h:3925
Assertion failed 'emitTypeSizes[TypeGet(type)] > 0' in 'System.GC:GetGCMemoryInfo(int):System.GCMemoryInfo' during 'Generate code' (IL size 75; hash 0xec24fb45; MinOpts)

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    arch-wasmWebAssembly architecturearea-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

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