Several x86 intrinsic APIs are "missing"

[tannergooding]

In the process of adding the APIs for #23315 (see dotnet/coreclr#15341), I found several non-scalar x86 intrinsic APIs that are "missing".

We should determine which of these need to be added and which were explicitly excluded.

int _mm_movemask_ps (__m128 a)                                      // movmskps

__m128d _mm_loadh_pd (__m128d a, double const* mem_addr)            // movhpd
__m128d _mm_loadl_pd (__m128d a, double const* mem_addr)            // movlpd
__m128i _mm_loadl_epi64 (__m128i const* mem_addr)                   // movq

void _mm_stream_si32 (int* mem_addr, int a)                         // movnti
void _mm_stream_si64 (__int64* mem_addr, __int64 a)                 // movnti

__m256i _mm256_permute2f128_si256 (__m256i a, __m256i b, int imm8)  // vperm2f128

__m256i _mm256_stream_load_si256 (__m256i const* mem_addr)          // vmovntdqa

// The following 8 have intrinsics which take an imm8 and emit the same underlying instruction
__m128i _mm_sll_epi16 (__m128i a, __m128i count)                    // psllw
__m128i _mm_sll_epi32 (__m128i a, __m128i count)                    // pslld
__m128i _mm_sll_epi64 (__m128i a, __m128i count)                    // psllq
__m128i _mm_sra_epi16 (__m128i a, __m128i count)                    // psraw
__m128i _mm_sra_epi32 (__m128i a, __m128i count)                    // psrad
__m128i _mm_srl_epi16 (__m128i a, __m128i count)                    // psrlw
__m128i _mm_srl_epi32 (__m128i a, __m128i count)                    // psrld
__m128i _mm_srl_epi64 (__m128i a, __m128i count)                    // psrlq

// The following 6 have the corresponding _mm256 forms exposed
__m128i _mm_sllv_epi32 (__m128i a, __m128i count)                   // vpsllvd
__m128i _mm_sllv_epi64 (__m128i a, __m128i count)                   // vpsllvq
__m128i _mm_srav_epi32 (__m128i a, __m128i count)                   // vpsravd
__m128i _mm_srlv_epi32 (__m128i a, __m128i count)                   // vpsrlvd
__m128i _mm_srlv_epi64 (__m128i a, __m128i count)                   // vpsrlvq

[tannergooding]

From the discussion so far on dotnet/coreclr#15341.

int _mm_movemask_ps (__m128 a) is missing from Sse. It was an oversight and the corresponding Sse2 intrinsic already exists.

__m256i _mm256_permute2f128_si256 (__m256i a, __m256i b, int imm8) is discouraged from use due to a data bypass penalty, but we may be able to complement the types to make the API simpler via Permute2x128<T>.

[tannergooding]

void _mm_stream_si32 (int* mem_addr, int a) and void _mm_stream_si64 (__int64* mem_addr, __int64 a) are streaming store for scalar types. There needs to be further thought about their usefulness

[tannergooding]

CC. @fiigii. Moved the discussion here so that dotnet/coreclr#15341 stays on track and isn't blocked by this.

[4creators]

// The following 8 have intrinsics which take an imm8 and emit the same underlying instruction
__m128i _mm_sll_epi16 (__m128i a, __m128i count)                    // psllw
__m128i _mm_sll_epi32 (__m128i a, __m128i count)                    // pslld
__m128i _mm_sll_epi64 (__m128i a, __m128i count)                    // psllq
__m128i _mm_sra_epi16 (__m128i a, __m128i count)                    // psraw
__m128i _mm_sra_epi32 (__m128i a, __m128i count)                    // psrad
__m128i _mm_srl_epi16 (__m128i a, __m128i count)                    // psrlw
__m128i _mm_srl_epi32 (__m128i a, __m128i count)                    // psrld
__m128i _mm_srl_epi64 (__m128i a, __m128i count)                    // psrlq

IMO we should implement them with imm8. This allows for faster code as call may skip Vector creation and setting shift values on Vector. The missing language feature for supporting immediate / compile constants parameters can be compensated with analyzer and attribute like previously discussed (I can implement support for this feature).

[4creators]

Ahh forgot it - we should have corresponding AVX/AVX2 instructions as well. They really can be very handy in many situations.

[karelz]

cc @CarolEidt @RussKeldorph

[4creators]

// The following 8 have intrinsics which take an imm8 and emit the same underlying instruction

Emitted instruction is not the same for imm8 and _mm128i / _mm256i arguments, encoding is different.

[tannergooding]

Emitted instruction is not the same for imm8 and _mm128i / _mm256i arguments, encoding is different.

The encoding is different, but it is still psll*, psra*, and psrl*, which is what I meant.

[4creators]

There is a large class of instructions missing: all that may take as an argument both SIMD register xmm, ymm or memory address i.e.:

__m128i _mm_add_epi64 (__m128i a,  __m128i b)
paddq xmm, xmm
public static Vector128<ulong> Add(Vector128<ulong> left, Vector128<ulong> right);
// missing
paddq xmm, m128
public static unsafe Vector128<ulong> Add(Vector128<ulong> left, ulong* right);
// or another form
public static unsafe Vector128<ulong> Add(Vector128<ulong> left, Vector128<ulong>* right);

it could be that there was Api Review decision to not implement these variants, than this would be to just remind what is missing by design

cc @tannergooding @fiigii

[mikedn]

public static unsafe Vector128 Add(Vector128 left, Vector128* right);

What for? You can just write Add(left, *pRight).

[4creators]

What for? You can just write Add(left, *pRight)

Providing RyuJIT will generate paddq xmm, m128 without separate load instruction.

[fiigii]

@4creators We do not expose these reg-mem/mem-reg instructions as intrinsics. The compiler will fold Load/Store into paddq xmm, m128. Please see the discussion dotnet/coreclr#15538 (comment)

[4creators]

@fiigii OK I have expected it was / could be by design.

[4creators]

@fiigii @tannergooding
Just went through SSE2 shift intrinsics again and based on the list from top post and my double check it seems we are missing:

1. the following logical shifts:

       /// <summary>
        /// __m128i _mm_sll_epi16 (__m128i a, __m128i count)
        /// </summary>
        public static Vector128<short> ShiftLeftLogical(Vector128<short> value, Vector128<short> count) => ShiftLeftLogical(value, count);
        /// <summary>
        /// __m128i _mm_sll_epi16 (__m128i a,  __m128i count)
        /// </summary>
        public static Vector128<ushort> ShiftLeftLogical(Vector128<ushort> value, Vector128<ushort> count) => ShiftLeftLogical(value, count);
        /// <summary>
        /// __m128i _mm_sll_epi32 (__m128i a,  __m128i count)
        /// </summary>
        public static Vector128<int> ShiftLeftLogical(Vector128<int> value, Vector128<int> count) => ShiftLeftLogical(value, count);
        /// <summary>
        /// __m128i _mm_sll_epi32 (__m128i a,  __m128i count)
        /// </summary>
        public static Vector128<uint> ShiftLeftLogical(Vector128<uint> value, Vector128<uint> count) => ShiftLeftLogical(value, count);
        /// <summary>
        /// __m128i _mm_sll_epi64 (__m128i a,  __m128i count)
        /// </summary>
        public static Vector128<long> ShiftLeftLogical(Vector128<long> value, Vector128<long> count) => ShiftLeftLogical(value, count);
        /// <summary>
        /// __m128i _mm_sll_epi64 (__m128i a,  __m128i count)
        /// </summary>
        public static Vector128<ulong> ShiftLeftLogical(Vector128<ulong> value, Vector128<ulong> count) => ShiftLeftLogical(value, count);
        /// <summary>
        /// __m128i _mm_srl_epi16 (__m128i a,  __m128i count)
        /// </summary>
        public static Vector128<short> ShiftRightLogical(Vector128<short> value, Vector128<short> count) => ShiftRightLogical(value, count);
        /// <summary>
        /// __m128i _mm_srl_epi16 (__m128i a,  __m128i count)
        /// </summary>
        public static Vector128<ushort> ShiftRightLogical(Vector128<ushort> value, Vector128<ushort> count) => ShiftRightLogical(value, count);
        /// <summary>
        /// __m128i _mm_srl_epi32 (__m128i a,  __m128i count)
        /// </summary>
        public static Vector128<int> ShiftRightLogical(Vector128<int> value, Vector128<int> count) => ShiftRightLogical(value, count);
        /// <summary>
        /// __m128i _mm_srl_epi32 (__m128i a,  __m128i count)
        /// </summary>
        public static Vector128<uint> ShiftRightLogical(Vector128<uint> value, Vector128<uint> count) => ShiftRightLogical(value, count);
        /// <summary>
        /// __m128i _mm_srl_epi64 (__m128i a,  __m128i count)
        /// </summary>
        public static Vector128<long> ShiftRightLogical(Vector128<long> value, Vector128<long> count) => ShiftRightLogical(value, count);
        /// <summary>
        /// __m128i _mm_srl_epi64 (__m128i a,  __m128i count)
        /// </summary>
        public static Vector128<ulong> ShiftRightLogical(Vector128<ulong> value, Vector128<ulong> count) => ShiftRightLogical(value, count);

2. the following right arithmetic shifts:

        /// <summary>
        /// __m128i _mm_sra_epi16 (__m128i a,  __m128i count)
        /// </summary>
        public static Vector128<short> ShiftRightArithmetic(Vector128<short> value, Vector128<short> count) => ShiftRightArithmetic(value, count);
        /// <summary>
        /// __m128i _mm_sra_epi32 (__m128i a,  __m128i count)
        /// </summary>
        public static Vector128<int> ShiftRightArithmetic(Vector128<int> value, Vector128<int> count) => ShiftRightArithmetic(value, count);

Can we have decision on implementing these APIs and get them merged?

[fiigii]

@4creators Thank you! Actually, I already have a fix on my local machine. Will upload tomorrow.