Assertion failed 'srcInterval->registerType == registerType' in 'JIT.HardwareIntrinsics.Arm.Helpers:BitwiseSelect(float,float,float):float' during 'Linear scan register alloc'

[BruceForstall]

Linux-arm64 random JitStress

https://dev.azure.com/dnceng/public/_build/results?buildId=1957444&view=ms.vss-test-web.build-test-results-tab&runId=50310504&resultId=107552&paneView=debug

+ cat /root/helix/work/workitem/u/SetStressModes_jitstress_random_2.sh
#!/usr/bin/env bash
export COMPlus_TieredCompilation=0
export COMPlus_DbgEnableMiniDump=1
export COMPlus_DbgMiniDumpName=$HELIX_DUMP_FOLDER/coredump.%d.dmp
export COMPlus_JitStress=3db

...

    JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part2_ro/AdvSimd_Part2_ro.sh [FAIL]
      
      Assert failure(PID 272 [0x00000110], Thread: 272 [0x0110]): Assertion failed 'srcInterval->registerType == registerType' in 'JIT.HardwareIntrinsics.Arm.Helpers:BitwiseSelect(float,float,float):float' during 'Linear scan register alloc' (IL size 29; hash 0x40376f3b; FullOpts)
      
          File: /__w/1/s/src/coreclr/jit/lsrabuild.cpp Line: 3531
          Image: /root/helix/work/correlation/corerun

@kunalspathak @dotnet/jit-contrib

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

Issue Details

---

Linux-arm64 random JitStress

https://dev.azure.com/dnceng/public/_build/results?buildId=1957444&view=ms.vss-test-web.build-test-results-tab&runId=50310504&resultId=107552&paneView=debug

+ cat /root/helix/work/workitem/u/SetStressModes_jitstress_random_2.sh
#!/usr/bin/env bash
export COMPlus_TieredCompilation=0
export COMPlus_DbgEnableMiniDump=1
export COMPlus_DbgMiniDumpName=$HELIX_DUMP_FOLDER/coredump.%d.dmp
export COMPlus_JitStress=3db

...

    JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_Part2_ro/AdvSimd_Part2_ro.sh [FAIL]
      
      Assert failure(PID 272 [0x00000110], Thread: 272 [0x0110]): Assertion failed 'srcInterval->registerType == registerType' in 'JIT.HardwareIntrinsics.Arm.Helpers:BitwiseSelect(float,float,float):float' during 'Linear scan register alloc' (IL size 29; hash 0x40376f3b; FullOpts)
      
          File: /__w/1/s/src/coreclr/jit/lsrabuild.cpp Line: 3531
          Image: /root/helix/work/correlation/corerun

@kunalspathak @dotnet/jit-contrib

Author:	BruceForstall
Assignees:	-
Labels:	arch-arm64, os-linux, JitStress, area-CodeGen-coreclr
Milestone:	7.0.0

[SingleAccretion]

Simple reproduction:

[MethodImpl(MethodImplOptions.NoInlining)]
private static float Problem(long x)
{
    var y = BitConverter.Int32BitsToSingle((int)x);
    Use(&x);
    JitUse(0);
    return y;
}

public static void Use<T>(T* arg) where T : unmanaged { }

[MethodImpl(MethodImplOptions.NoInlining)]
public static void JitUse<T>(T arg) { }

I think it's just this:

diff --git a/src/coreclr/jit/lsrabuild.cpp b/src/coreclr/jit/lsrabuild.cpp
index 21477e21302..089f4c27dec 100644
--- a/src/coreclr/jit/lsrabuild.cpp
+++ b/src/coreclr/jit/lsrabuild.cpp
@@ -3524,11 +3524,11 @@ int LinearScan::BuildStoreLoc(GenTreeLclVarCommon* storeLoc)
     else if (op1->isContained() && op1->OperIs(GT_BITCAST))
     {
         GenTree*     bitCastSrc   = op1->gtGetOp1();
-        RegisterType registerType = bitCastSrc->TypeGet();
+        RegisterType registerType = regType(bitCastSrc);
         singleUseRef              = BuildUse(bitCastSrc, allRegs(registerType));

         Interval* srcInterval = singleUseRef->getInterval();
-        assert(srcInterval->registerType == registerType);
+        assert(regType(srcInterval->registerType) == registerType);
         srcCount = 1;
     }

[kunalspathak]

Thanks @SingleAccretion . I tried that fix and it works. Do you know if this was because of some recent changes to BITCAST that exposed it?

[SingleAccretion]

Do you know if this was because of some recent changes to BITCAST that exposed it?

Probably #71567. The method in question uses the BitConverter APIs.