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[LSRA][RyuJIT] Consider merging allocating free & busy regs #9399

@CarolEidt

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@CarolEidt

Currently, LSRA iterates over all the free registers, and then iterates again if it has to find a register to spill. It would probably be more efficient, as well as more effective, to combine these passes. In particular, it would avoid the situation where we make a bad register choice for a critical Interval simply because it is the only free register, when it may be better to spill a less important Interval.
In particular, it seems like this may be the best approach to address #8846.

category:cq
theme:register-allocator
skill-level:expert
cost:medium

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    area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMItenet-performancePerformance related issue

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