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[RyuJIT] Update the emitter for VEX-encoded SSE4.1/4.2 instructions with containment #9697

@fiigii

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@fiigii

Detected this issue from dotnet/coreclr#16287.

With VEX-encdoing, certain SSE4.1/SSE4.2 instructions (vpcmpeqq) have incorrect encoding on INS reg, reg, mem form.
For example, vpcmpeqq ymm7, ymm6, ymmword ptr[rax] (ECS:6, ACS:5) is compiled to

C4 E2 4D 39 38
         ^

but the correct encoding should be

C4 E2 4D 29 38
         ^

The opcode of vpcmpeqq (66 0F 38 29) seems accidently changed.

Subset of https://github.com/dotnet/coreclr/issues/15908
I will look into this issue after dotnet/coreclr#16249 gets merged.

cc @CarolEidt @tannergooding

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area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI

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