Update lsra to not mark op2 as delay free for certain RMW nodes

[tannergooding]

For nodes with RMW semantics, we are currently setting op2 as delayFree in a number of scenarios: https://github.com/dotnet/coreclr/blob/master/src/jit/lsraxarch.cpp#L659

This can cause "poor" codegen in certain scenarios, such as when op1 and op2 are the same value (i.e. the same local) and where op2 is the "final use" for that value.

One example of this is:

public static Vector128<long> Test2(long value)
{
    var tmp = Sse2.ConvertScalarToVector128Int64(value);
    return Sse2.UnpackLow(tmp, tmp);
}

Where this currently (with dotnet/coreclr#16808) generates:

66480F6EC2           movd     xmm0, rdx
0F28C8               movaps   xmm1, xmm0
660F6CC8             punpcklqdq xmm1, xmm0
0F1109               movups   xmmword ptr [rcx], xmm1
488BC1               mov      rax, rcx

Not setting delay free for op2 allows us to elide the unneeded copy and instead generate:

66480F6EC2           movd     xmm0, rdx
660F6CC0             punpcklqdq xmm0, xmm0
0F1101               movups   xmmword ptr [rcx], xmm0
488BC1               mov      rax, rcx

category:cq
theme:register-allocator
skill-level:intermediate
cost:small

[tannergooding]

FYI. @CarolEidt, @dotnet/jit-contrib

[mikedn]

This can probably be solved by treating any binop(x, x) as if binop is commutative even when it is not.

[CarolEidt]

This may be fixed by PR #43116

[kunalspathak]

I can confirm that we see the expected code:

       vmovd    xmm0, rdx
       vpunpcklqdq xmm0, xmm0, xmm0
       vmovupd  xmmword ptr [rcx], xmm0
       mov      rax, rcx

[kunalspathak]

With COMPlus_EnableAVX=0, we still get inferior code:

       movd     xmm0, rdx
       movaps   xmm1, xmm0
       punpcklqdq xmm1, xmm0
       movups   xmmword ptr [rcx], xmm1
       mov      rax, rcx