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Arm64 SVE: Fix assert checks in SVE LDR/STR #119528

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Merged
jakobbotsch merged 1 commit into from
Sep 10, 2025
Merged

Arm64 SVE: Fix assert checks in SVE LDR/STR #119528

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8 changes: 4 additions & 4 deletions src/coreclr/jit/emitarm64sve.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2666,8 +2666,6 @@ void emitter::emitInsSve_R_R_I(instruction ins,
assert(insOptsNone(opt));
assert(isScalableVectorSize(size));
assert(isGeneralRegister(reg2)); // nnnnn
assert(isValidSimm<9>(imm)); // iii
// iiiiii
assert(insScalableOptsNone(sopt));

// imm is the number of bytes to offset by. The instruction requires a multiple of the
Expand All @@ -2686,6 +2684,8 @@ void emitter::emitInsSve_R_R_I(instruction ins,
imm = 0;
}

assert(isValidSimm<9>(imm));

if (isVectorRegister(reg1))
{
fmt = IF_SVE_IE_2A;
Expand All @@ -2701,8 +2701,6 @@ void emitter::emitInsSve_R_R_I(instruction ins,
assert(insOptsNone(opt));
assert(isScalableVectorSize(size));
assert(isGeneralRegister(reg2)); // nnnnn
assert(isValidSimm<9>(imm)); // iii
// iiiiii
assert(insScalableOptsNone(sopt));

// imm is the number of bytes to offset by. The instruction requires a multiple of the
Expand All @@ -2721,6 +2719,8 @@ void emitter::emitInsSve_R_R_I(instruction ins,
imm = 0;
}

assert(isValidSimm<9>(imm));

if (isVectorRegister(reg1))
{
fmt = IF_SVE_JH_2A;
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