JIT: Fix disasm of reg to reg SIMD narrowing/widening instructions

[saucecontrol]

Fixes #126363

This re-works the disasm for reg to reg instructions to cover some additional cases and make it a bit more consistent.

Many of the widening and narrowing instructions were showing the same size for source and target register.

Diff for the current vector byte multiply implementation:

        62F17C481002         vmovups  zmm0, zmmword ptr [rdx]
        62F17C4828C8         vmovaps  zmm1, zmm0
-       62F27D4820C9         vpmovsxbw zmm1, zmm1
+       62F27D4820C9         vpmovsxbw zmm1, ymm1
        62D17C481010         vmovups  zmm2, zmmword ptr [r8]
        62F17C4828DA         vmovaps  zmm3, zmm2
-       62F27D4820DB         vpmovsxbw zmm3, zmm3
+       62F27D4820DB         vpmovsxbw zmm3, ymm3
        62F16548D5C9         vpmullw  zmm1, zmm3, zmm1
-       62F27E4830C9         vpmovwb  zmm1, zmm1
+       62F27E4830C9         vpmovwb  ymm1, zmm1
        62F37D483BC001       vextracti32x8 ymm0, zmm0, 1
-       62F27D4820C0         vpmovsxbw zmm0, zmm0
+       62F27D4820C0         vpmovsxbw zmm0, ymm0
        62F37D483BD201       vextracti32x8 ymm2, zmm2, 1
-       62F27D4820D2         vpmovsxbw zmm2, zmm2
+       62F27D4820D2         vpmovsxbw zmm2, ymm2
        62F16D48D5C0         vpmullw  zmm0, zmm2, zmm0
-       62F27E4830C0         vpmovwb  zmm0, zmm0
+       62F27E4830C0         vpmovwb  ymm0, zmm0
        62F375483AC001       vinserti32x8 zmm0, zmm1, ymm0, 1
        62F17C481101         vmovups  zmmword ptr [rcx], zmm0
        488BC1               mov      rax, rcx
        C5F877               vzeroupper 
        C3                   ret      

This also catches a few cases where embedded rounding was not included in the disasm. ex:

-    vcvtss2si eax, xmm0
+    vcvtss2si eax, xmm0 {rd-sae}

Confirmed with local jit-diff that there are no text changes aside from the above intended ones.

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[Copilot]

Pull request overview

This PR updates the xarch JIT instruction disassembly formatting to correctly display operand register widths for SIMD widening/narrowing instructions (e.g., showing ymm sources for zmm widening, and ymm targets for zmm narrowing), addressing incorrect/invalid-looking disasm output reported in #126363.

Changes:

• Adjust disasm operand-size selection for reg-to-reg SIMD widening and narrowing/conversion instructions by deriving source/target emitAttr from the instruction size.
• Refactor IF_RRW_* reg/reg display logic to compute tgtAttr/srcAttr and print via a single shared path (preserving special-case handling for bt and APX NDD shift forms).
• Add vcvtps2ph handling in the reg/reg/imm display path to account for differing source/target widths.

[saucecontrol]

cc @dotnet/jit-contrib

No code diffs, just disasm text fixes.

[Copilot]

Pull request overview

Copilot reviewed 1 out of 1 changed files in this pull request and generated no new comments.

[JulieLeeMSFT]

/ba-g all known issues.