Skip to content

[RISC-V] Use fine-grained fence variants for memory barriers #126566

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
jakobbotsch merged 2 commits into from
Apr 17, 2026
+19 −5
Merged

[RISC-V] Use fine-grained fence variants for memory barriers #126566

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
398c025
[RISC-V] Use fine-grained fence variants for memory barriers
JamieMagee Apr 6, 2026
1cb1191
Merge branch 'main' into dev/riscv64-fine-grained-barriers
jakobbotsch Apr 14, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
20 changes: 16 additions & 4 deletions src/coreclr/jit/codegenriscv64.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2204,7 +2204,6 @@ void CodeGen::genCodeForCpObj(GenTreeBlk* cpObjNode)
if (cpObjNode->IsVolatile())
{
// issue a INS_BARRIER_RMB after a volatile CpObj operation
Comment thread
jakobbotsch marked this conversation as resolved.
// TODO-RISCV64: there is only BARRIER_FULL for RISCV64.
instGen_MemoryBarrier(BARRIER_FULL);
}

Expand Down Expand Up @@ -6257,7 +6256,7 @@ void CodeGen::genJumpToThrowHlpBlk_la(
// instGen_MemoryBarrier: Emit a MemoryBarrier instruction
//
// Arguments:
// barrierKind - kind of barrier to emit (Only supports the Full now!! This depends on the CPU).
// barrierKind - kind of barrier to emit
//
// Notes:
// All MemoryBarriers instructions can be removed by DOTNET_JitNoMemoryBarriers=1
Expand All @@ -6271,8 +6270,21 @@ void CodeGen::instGen_MemoryBarrier(BarrierKind barrierKind)
}
#endif // DEBUG

// TODO-RISCV64: Use the exact barrier type depending on the CPU.
GetEmitter()->emitIns_I(INS_fence, EA_4BYTE, INS_BARRIER_FULL);
insBarrier barrier;
switch (barrierKind)
{
case BARRIER_LOAD_ONLY:
barrier = INS_BARRIER_LOAD_ONLY;
break;
case BARRIER_STORE_ONLY:
barrier = INS_BARRIER_STORE_ONLY;
break;
default:
barrier = INS_BARRIER_FULL;
break;
}

GetEmitter()->emitIns_I(INS_fence, EA_4BYTE, barrier);
Comment thread
JamieMagee marked this conversation as resolved.
}

/*-----------------------------------------------------------------------------
Expand Down
4 changes: 3 additions & 1 deletion src/coreclr/jit/instr.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -566,7 +566,9 @@ enum insOpts : unsigned

enum insBarrier : unsigned
{
INS_BARRIER_FULL = 0x33,
INS_BARRIER_FULL = 0x33, // fence rw, rw
INS_BARRIER_LOAD_ONLY = 0x23, // fence r, rw
INS_BARRIER_STORE_ONLY = 0x31, // fence rw, w
};
#elif defined(TARGET_WASM)
enum insOpts : unsigned
Expand Down
Loading