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Cleanup the xarch perfscore handling #127109

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Merged
tannergooding merged 6 commits into from
Apr 19, 2026
Merged

Cleanup the xarch perfscore handling #127109

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57109ce
Cleanup the xarch perfscore handling
tannergooding Apr 18, 2026
d77ea23
Fix one of the throughput definitions
tannergooding Apr 18, 2026
0c796b1
Fix a throughput comment
tannergooding Apr 18, 2026
c4aa3e0
Respond to PR feedback
tannergooding Apr 18, 2026
171c766
Potential fix for pull request finding
tannergooding Apr 18, 2026
d47756a
Fix another comment
tannergooding Apr 18, 2026
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22 changes: 19 additions & 3 deletions src/coreclr/jit/emit.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2057,13 +2057,17 @@ class emitter
#define PERFSCORE_THROUGHPUT_8C 8.0f // slower - 8 cycles
#define PERFSCORE_THROUGHPUT_9C 9.0f // slower - 9 cycles
#define PERFSCORE_THROUGHPUT_10C 10.0f // slower - 10 cycles
#define PERFSCORE_THROUGHPUT_11C 10.0f // slower - 10 cycles
#define PERFSCORE_THROUGHPUT_11C 11.0f // slower - 11 cycles
#define PERFSCORE_THROUGHPUT_12C 12.0f // slower - 12 cycles
#define PERFSCORE_THROUGHPUT_13C 13.0f // slower - 13 cycles
#define PERFSCORE_THROUGHPUT_14C 14.0f // slower - 13 cycles
#define PERFSCORE_THROUGHPUT_16C 16.0f // slower - 13 cycles
#define PERFSCORE_THROUGHPUT_14C 14.0f // slower - 14 cycles
#define PERFSCORE_THROUGHPUT_16C 16.0f // slower - 16 cycles
#define PERFSCORE_THROUGHPUT_18C 18.0f // slower - 18 cycles
#define PERFSCORE_THROUGHPUT_19C 19.0f // slower - 19 cycles
#define PERFSCORE_THROUGHPUT_25C 25.0f // slower - 25 cycles
#define PERFSCORE_THROUGHPUT_32C 32.0f // slower - 32 cycles
#define PERFSCORE_THROUGHPUT_33C 33.0f // slower - 33 cycles
#define PERFSCORE_THROUGHPUT_36C 36.0f // slower - 36 cycles
#define PERFSCORE_THROUGHPUT_50C 50.0f // slower - 50 cycles
#define PERFSCORE_THROUGHPUT_52C 52.0f // slower - 52 cycles
#define PERFSCORE_THROUGHPUT_57C 57.0f // slower - 57 cycles
Expand All @@ -2088,11 +2092,18 @@ class emitter
#define PERFSCORE_LATENCY_14C 14.0f
#define PERFSCORE_LATENCY_15C 15.0f
#define PERFSCORE_LATENCY_16C 16.0f
#define PERFSCORE_LATENCY_17C 17.0f
#define PERFSCORE_LATENCY_18C 18.0f
#define PERFSCORE_LATENCY_20C 20.0f
#define PERFSCORE_LATENCY_22C 22.0f
#define PERFSCORE_LATENCY_23C 23.0f
#define PERFSCORE_LATENCY_26C 26.0f
#define PERFSCORE_LATENCY_28C 28.0f
#define PERFSCORE_LATENCY_31C 31.0f
#define PERFSCORE_LATENCY_32C 32.0f
#define PERFSCORE_LATENCY_33C 33.0f
#define PERFSCORE_LATENCY_41C 41.0f
#define PERFSCORE_LATENCY_45C 45.0f
#define PERFSCORE_LATENCY_62C 62.0f
#define PERFSCORE_LATENCY_69C 69.0f
#define PERFSCORE_LATENCY_105C 105.0f
Expand All @@ -2105,6 +2116,11 @@ class emitter

#if defined(TARGET_XARCH)

// a read has 2x (0.5) throughput, while a write has 1C (1.0) throughput
#define PERFSCORE_THROUGHPUT_RD PERFSCORE_THROUGHPUT_2X
#define PERFSCORE_THROUGHPUT_WR PERFSCORE_THROUGHPUT_1C
#define PERFSCORE_THROUGHPUT_RW PERFSCORE_THROUGHPUT_1C

// a read,write or modify from stack location, possible def to use latency from L0 cache
#define PERFSCORE_LATENCY_RD_STACK PERFSCORE_LATENCY_2C
#define PERFSCORE_LATENCY_WR_STACK PERFSCORE_LATENCY_2C
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