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JIT: gate Vector512.ConvertToInt32(Native) on AVX-512 #127499

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JIT: gate Vector512.ConvertToInt32(Native) on AVX-512 #127499

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Copilot Apr 28, 2026
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JIT: gate Vector512.ConvertToInt32(Native) on AVX-512 support
Copilot Apr 28, 2026
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4 changes: 2 additions & 2 deletions src/coreclr/jit/gentree.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -23127,7 +23127,7 @@ GenTree* Compiler::gtNewSimdCvtNode(
assert(varTypeIsIntegral(simdTargetBaseType));

#if defined(TARGET_XARCH)
assert(compIsaSupportedDebugOnly(InstructionSet_AVX512) || (simdTargetBaseType == TYP_INT));
assert(compIsaSupportedDebugOnly(InstructionSet_AVX512) || ((simdTargetBaseType == TYP_INT) && (simdSize != 64)));

GenTree* fixupVal;

Expand Down Expand Up @@ -23258,7 +23258,7 @@ GenTree* Compiler::gtNewSimdCvtNativeNode(
NamedIntrinsic hwIntrinsicID = NI_Illegal;

#if defined(TARGET_XARCH)
assert(compIsaSupportedDebugOnly(InstructionSet_AVX512) || (simdTargetBaseType == TYP_INT));
assert(compIsaSupportedDebugOnly(InstructionSet_AVX512) || ((simdTargetBaseType == TYP_INT) && (simdSize != 64)));

switch (simdSourceBaseType)
{
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14 changes: 14 additions & 0 deletions src/coreclr/jit/hwintrinsicxarch.cpp
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Expand Up @@ -1853,6 +1853,13 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_FLOAT);

if ((simdSize == 64) && !compOpportunisticallyDependsOn(InstructionSet_AVX512))
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@MichalPetryka MichalPetryka Apr 28, 2026

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Does Vector256 not need AVX here too?

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@EgorBo EgorBo Apr 28, 2026

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No - Vector256.ConvertToInt32 is already gated upstream in lookupId (returns NI_Illegal on no-AVX hosts, falling back to the managed body). On AVX-without-AVX2 it's allowed via HW_Flag_AvxOnlyCompatible and gtNewSimdCvtNativeNode emits a plain AVX vcvttps2dq ymm. Vector512 is the odd one out because there's no non-AVX-512 single-op equivalent for the 64-byte conversion.

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@tannergooding tannergooding Apr 28, 2026

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This should also be gated upstream, however, as we shouldn't even be getting simdSize == 64 if its not accelerated.

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@tannergooding tannergooding Apr 28, 2026

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Right here: https://github.com/dotnet/runtime/blob/main/src/coreclr/jit/hwintrinsic.cpp#L1371-L1377

So we should never even be producing an intrinsic ID for this in the first place.

{
// Vector512 float->int conversion requires AVX-512 for the native
// truncation instruction. Fall back to the managed implementation.
break;
}

op1 = impSIMDPopStack();
retNode = gtNewSimdCvtNode(retType, op1, TYP_INT, simdBaseType, simdSize);
break;
Expand All @@ -1870,6 +1877,13 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
break;
}

if ((simdSize == 64) && !compOpportunisticallyDependsOn(InstructionSet_AVX512))
{
// Vector512 float->int conversion requires AVX-512 for the native
// truncation instruction. Fall back to the managed implementation.
break;
}

op1 = impSIMDPopStack();
retNode = gtNewSimdCvtNativeNode(retType, op1, TYP_INT, simdBaseType, simdSize);
break;
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