Fix PerfScore inconcistencies

[pentp]

• Hide write latency for memAccessKind == PERFSCORE_MEMORY_READ_WRITE like for PERFSCORE_MEMORY_WRITE.
• Fix memory access latencies for many instructions that previously didn't add the instruction latency to memory access latency or overwrote memory latency with register access latency.
• Adjust some instruction latencies for YMM register size.
• Fix latencies for a lot of instructions by using more precise uops.info data.

Fixes #49647

[kunalspathak]

@dotnet/jit-contrib , @briansull

[kunalspathak]

                            result.insLatency = PERFSCORE_LATENCY_3C;

Need += here?

---

Refers to: src/coreclr/jit/emitxarch.cpp:14921 in 51c7ec6. [](commit_id = 51c7ec6, deletion_comment = False)

[kunalspathak]

            result.insLatency = PERFSCORE_LATENCY_23C;

+= ?

---

Refers to: src/coreclr/jit/emitxarch.cpp:15266 in 51c7ec6. [](commit_id = 51c7ec6, deletion_comment = False)

[kunalspathak]

Thank you for fixing. I have added few questions.

[kunalspathak]

Why we are hiding latency for PERFSCORE_MEMORY_READ_WRITE as well? Is the assumption in the comment below holds true even for PERFSCORE_MEMORY_READ_WRITE?

[pentp]

We're only hiding the write part of R/W here so that add [mem], x doesn't end up with a higher perfscore than mov reg, [mem]; add reg, x; mov [mem], reg.
The assumption below is now assumed to be true for both writes and I've adjusted some of the instruction latencies to reflect that.

[kunalspathak]

Good catch.

[kunalspathak]

Similarly, need to also do it for xchg, call, fstp

[pentp]

Not sure how much memory latency affects call [mem], uops.info doesn't have any info on this. It's probably going to be less than the 3C from throughput, so not worth changing it here.

[pentp]

fld and fstp I'm also not sure about what's the correct value (again no data at uops.info).

[kunalspathak]

Do we need to update Model the memory latency to not count this twice?

[pentp]

This isn't counted twice, this 2/3C latency is in addition to the modeled memory access base latency (i.e., mov latency). To put it another way, mov rax, [mem] has lower latency than movdqa ymm, [mem].

[pentp]

                            result.insLatency = PERFSCORE_LATENCY_3C;

Need += here?

Refers to: src/coreclr/jit/emitxarch.cpp:14921 in 51c7ec6. [](commit_id = 51c7ec6, deletion_comment = False)

This is for lea which should ignore (overwrite) memory access latency.

            result.insLatency = PERFSCORE_LATENCY_23C;

+= ?

Refers to: src/coreclr/jit/emitxarch.cpp:15266 in 51c7ec6. [](commit_id = 51c7ec6, deletion_comment = False)

xchg [mem], reg latency is complicated/bad, could be anywhere between 10 and 45 depending on the exact instruction form+sequence and CPU, so probably this is just an average and the instruction should be avoided if possible.

[kunalspathak]

LGTM. Thanks for your responses.