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Arm64: Memory barrier improvements #62895

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Merged
kunalspathak merged 4 commits into from
Jan 5, 2022
Merged

Arm64: Memory barrier improvements #62895

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74f24f3
Use ishst instead of ish
kunalspathak Dec 13, 2021
d2d6d70
Do not contain address of volatile fields
kunalspathak Dec 16, 2021
687277b
Do not contain address only for Arm64
kunalspathak Dec 17, 2021
c9267a5
Remove ishst
kunalspathak Jan 4, 2022
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3 changes: 3 additions & 0 deletions src/coreclr/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3280,6 +3280,9 @@ void CodeGen::genCodeForStoreInd(GenTreeStoreInd* tree)
else
{
// issue a full memory barrier before a volatile StInd
// Note: We cannot issue store barrier ishst because it is a weaker barrier.
// The loads can get rearranged around the barrier causing to read wrong
// value.
instGen_MemoryBarrier();
}
}
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8 changes: 8 additions & 0 deletions src/coreclr/jit/gentree.cpp
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Expand Up @@ -4083,6 +4083,14 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
}
}
}
#ifdef TARGET_ARM64
if (tree->gtFlags & GTF_IND_VOLATILE)
{
// For volatile store/loads when address is contained we always emit `dmb`
// if it's not - we emit one-way barriers i.e. ldar/stlr
doAddrMode = false;
}
#endif // TARGET_ARM64
if (doAddrMode && gtMarkAddrMode(addr, &costEx, &costSz, tree->TypeGet()))
{
goto DONE;
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