LiteEthMACSRAMReader: TX timestamps never get written to the status FIFO

[nickyu42]

I'm working on a PTP implementation running on a custom board with LiteX+LiteEth, on packet transmit I need the timestamp in order to calculate path delays, however the timestamp register is never pushed to the status FIFO due to stat_fifo.valid being set on a state that does not exist (L272, END), I have changed this to TERMINATE, which works.

liteeth/liteeth/mac/sram.py

Lines 243 to 275 in 0502874

	self.fsm = fsm = FSM(reset_state="IDLE")
	fsm.act("IDLE",
	If(cmd_fifo.source.valid,
	read.eq(1),
	NextValue(length, dw//8),
	NextState("READ")
	)
	)
	fsm.act("READ",
	source.valid.eq(1),
	source.last.eq(length >= cmd_fifo.source.length),
	If(source.ready,
	read.eq(1),
	NextValue(length, length + dw//8),
	If(source.last,
	NextState("TERMINATE")
	)
	)
	)
	fsm.act("TERMINATE",
	NextValue(length, 0),
	self.ev.done.trigger.eq(1),
	cmd_fifo.source.ready.eq(1),
	NextState("IDLE")
	)
	if timestamp is not None:
	# Latch Timestamp on start of outgoing packet.
	self.sync += If(length == 0, stat_fifo.sink.timestamp.eq(timestamp))
	self.comb += stat_fifo.sink.valid.eq(fsm.ongoing("END"))
	self.comb += stat_fifo.sink.slot.eq(cmd_fifo.source.slot)
	# Trigger event when Status FIFO has contents (Override FSM assignment).
	self.comb += self.ev.done.trigger.eq(stat_fifo.source.valid)

Additionally, the EventManager's trigger signal is not overwritten as the comment states, in the generated verilog the FSM's statement (self.ev.done.trigger.eq(1)) is placed after the combinatorial statement. See main_ethmac_sram121_trigger in the following snippet:

always @(*) begin
    builder_liteethmac_liteethmacsramreader_next_state <= 2'd0;
    main_ethmac_is_ongoing <= 1'd0;
    main_ethmac_read <= 1'd0;
    main_ethmac_sram121_trigger <= 1'd0;
    main_ethmac_sram136_length_liteethmac_liteethmacsramreader_next_value <= 11'd0;
    main_ethmac_sram136_length_liteethmac_liteethmacsramreader_next_value_ce <= 1'd0;
    main_ethmac_sram144_source_ready <= 1'd0;
    main_ethmac_sram91_source_valid <= 1'd0;
    main_ethmac_sram94_source_last <= 1'd0;
    main_ethmac_sram121_trigger <= main_ethmac_sram180_source_valid;
    builder_liteethmac_liteethmacsramreader_next_state <= builder_liteethmac_liteethmacsramreader_state;
    case (builder_liteethmac_liteethmacsramreader_state)
        1'd1: begin
            main_ethmac_sram91_source_valid <= 1'd1;
            main_ethmac_sram94_source_last <= (main_ethmac_sram136_length >= main_ethmac_sram148_source_payload_length);
            if (main_ethmac_sram92_source_ready) begin
                main_ethmac_read <= 1'd1;
                main_ethmac_sram136_length_liteethmac_liteethmacsramreader_next_value <= (main_ethmac_sram136_length + 3'd4);
                main_ethmac_sram136_length_liteethmac_liteethmacsramreader_next_value_ce <= 1'd1;
                if (main_ethmac_sram94_source_last) begin
                    builder_liteethmac_liteethmacsramreader_next_state <= 2'd2;
                end
            end
        end
        2'd2: begin
            main_ethmac_sram136_length_liteethmac_liteethmacsramreader_next_value <= 1'd0;
            main_ethmac_sram136_length_liteethmac_liteethmacsramreader_next_value_ce <= 1'd1;
            main_ethmac_sram121_trigger <= 1'd1;
            main_ethmac_sram144_source_ready <= 1'd1;
            builder_liteethmac_liteethmacsramreader_next_state <= 1'd0;
            main_ethmac_is_ongoing <= 1'd1;
        end
        default: begin
            if (main_ethmac_sram143_source_valid) begin
                main_ethmac_read <= 1'd1;
                main_ethmac_sram136_length_liteethmac_liteethmacsramreader_next_value <= 3'd4;
                main_ethmac_sram136_length_liteethmac_liteethmacsramreader_next_value_ce <= 1'd1;
                builder_liteethmac_liteethmacsramreader_next_state <= 1'd1;
            end
        end
    endcase
end