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@Xiretza Xiretza commented Jun 29, 2022

The hardware and cpu ports' valid signals can not be made dependent on their own ready signals, since this creates combinatorial loops. This should be unnecessary anyway though, the only thing that matters is that the valid signal is not asserted while the other sink is not ready.

The hardware and cpu ports' valid signals can not be made dependent on
their own ready signals, since this creates combinatorial loops. This
should be unnecessary anyway though, the only thing that matters is that
the valid signal is not asserted while the other sink is not ready.
@Xiretza Xiretza marked this pull request as draft June 30, 2022 04:54
@Xiretza
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Xiretza commented Jun 30, 2022

I haven't had time to actualy test this yet, so I'll keep it a draft for now unless you're sure this is correct.

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Thanks @Xiretza, I'll study it in the next days.

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