Make LiteEthMACCore clock domain crossing TX/RX fifo depths configurable

[rprinz08]

Commit 72dd7bf reduced buffering from 64 to 32 which affects a design. So make it configurable to be flexible.

[enjoy-digital]

Thanks @rprinz08, can you provide more information on the affected design? (especially the sys_clk_freq of the SoC and speed of the Ethernet Link)

[rprinz08]

The design runs with sys_clk_freq=100MHz and uses a LiteEthPHYRMII with external 50MHz clock and a LiteEthMACCore. Interface runs at 100Mbit full duplex. With reduced CDC depth, no last signal is issued by LiteEthMACCore source when a network packet was completely received.

[enjoy-digital]

@rprinz08 Thanks for the info. Rather than exposing the FIFO depths, I would like to understand the real cause of the issue but it seems design similar to yours are working correctly (ex the Digilent Arty has a very similar config: 100MHz sys_clk_freq, RMII PHY, 100Mbit full duplex). Could you provide a way to observe the issue so that I investigate on the Digilent Arty? Thanks.

[rprinz08]

Thx for the answer. I will create an example design sohwing the problem (in the next weeks). It actually happens when capturing longer (>1000 bytes) packets into a memory for further processing.